Patents by Inventor Young-rae Park
Young-rae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973584Abstract: This application relates to a noise signal generating apparatus. In one aspect, the apparatus includes a bandwidth expansion unit configured to generate a noise signal having a second bandwidth by expanding a noise source signal having a first bandwidth to the second bandwidth that is greater than the first bandwidth. The apparatus may also include a randomization unit configured to perform randomization and output the generated noise signal having the second bandwidth.Type: GrantFiled: July 15, 2021Date of Patent: April 30, 2024Assignee: Agency for Defense DevelopmentInventors: Jaewon Chang, Jeong Ho Ryu, Joo Rae Park, Young Ju Park, Byeong Nam Lee
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Publication number: 20240123760Abstract: A method for manufacturing a vehicle wheel includes: a casting process of manufacturing the wheel in a one-piece body having a forming end and a temporary flange protruding at inner and outer sides of the wheel, respectively, wherein the one-piece body further includes a resonance chamber forming groove; a primary shape machining process of forming a stepped part at an outer circumferential side of the resonance chamber forming groove; a flow forming process of bending the forming end to be seated on the stepped part; a friction stir welding process of integrally bonding a portion where the forming end and the stepped part are in close contact with each other; a fine machining process of removing the temporary flange; and a sound-absorbing hole machining process of forming a sound-absorbing hole for communicating between the resonance chamber and an interior space of a tire in the forming end.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Applicants: Hyundai Motor Company, KIA CORPORATION, Hyundai Sungwoo Casting Co., Ltd.Inventors: Jun Min LEE, Young Chan KIM, Min Soo KIM, Young Rae JO, Young Il KIM, Sang Bum PARK, Chang Hak YOO
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Publication number: 20240113403Abstract: The present disclosure relates to an electrolyte injection system, and the electrolyte injection system is a system for injecting an electrolyte solution into a pouch in which an electrode assembly is embedded, the electrolyte injection system comprising: an injection pipe for injecting an electrolyte solution; an electrolyte solution supply portion supplying an electrolyte solution; and a manifold portion connecting an injection pipe and an electrolyte solution supply portion to prevent a reverse flow of the electrolyte solution and ensure precision of injection amount so that a large amount of electrolyte solution may be accurately and rapidly injected.Type: ApplicationFiled: July 27, 2023Publication date: April 4, 2024Inventors: Jae Min RYU, Sang Jun PARK, Kang San KIM, Ji Eun AHN, Young Rae OH
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Publication number: 20220266649Abstract: A driving module of an autonomous mobile robot is provided. The driving module includes a first wheel in constant contact with ground or road surface and having a first rotational axis; second and third wheels constrained in their positions relative to each other; a rear bar on which a second rotational axis of the second wheel is positioned at one end, an upper axis portion is provided at the other end, and an intermediate axis portion is provided in the middle; a front bar on which a third rotational axis of the third wheel is positioned at one end, in which the other end of the front bar is pivotably coupled to the intermediate axis portion; and a suspension unit of which one end is pivotably coupled to the upper axis portion and the other end is pivotably coupled to the third rotational axis or the front bar.Type: ApplicationFiled: May 11, 2022Publication date: August 25, 2022Applicant: ROBOTIS CO, LTD.Inventors: Byoung Soo KIM, In Young HA, Woo Sik YANG, Han Cheol CHO, Young Rae PARK
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Patent number: 7244649Abstract: A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.Type: GrantFiled: December 9, 2004Date of Patent: July 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Dong Lee, Chang-Ki Hong, Young-Rae Park
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Publication number: 20070155178Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.Type: ApplicationFiled: March 1, 2007Publication date: July 5, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-rae Park, Jung-yup Kim, Bo-un Yoon, Kwang-bok Kim, Jae-phill Boo, Jong-won Lee, Sang-rok Hah, Kyung-hyun Kim, Chang-ki Hong
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Patent number: 7196010Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.Type: GrantFiled: August 12, 2003Date of Patent: March 27, 2007Assignee: Samsung Electronics, Co., Ltd.Inventors: Young-rae Park, Jung-yup Kim, Bo-un Yoon, Kwang-bok Kim, Jae-phil Boo, Jong-won Lee, Sang-rok Hah, Kyung-hyun Kim, Chang-ki Hong
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Publication number: 20050272218Abstract: A method of forming a cylindrical lower electrode of a capacitor in which metal is used as a lower electrode of a capacitor. A metal capping layer is used in order to protect the inner walls of the cylindrical metal lower electrode. A sacrificial insulating layer is patterned to form an aperture for forming the lower electrode. A metal lower electrode layer and the metal capping layer are sequentially formed. In order to electrically separate adjacent metal lower electrodes from each other, the metal capping layer and the metal lower electrode layer are simultaneously planarized until the sacrificial insulating layer is exposed. The sacrificial insulating layer and the metal capping layer that resides in the aperture are removed such that the cylindrical metal lower electrode having inner and outer walls is completed.Type: ApplicationFiled: June 3, 2005Publication date: December 8, 2005Inventors: Young-Rae Park, Young-Ho Koh, Chang-Ki Hong
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Publication number: 20050130385Abstract: A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.Type: ApplicationFiled: December 9, 2004Publication date: June 16, 2005Inventors: Jae-Dong Lee, Chang-Ki Hong, Young-Rae Park
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Patent number: 6858452Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.Type: GrantFiled: October 17, 2003Date of Patent: February 22, 2005Assignee: Samsung Electronics Co., LTDInventors: Jeong-heon Park, Chang-ki Hong, Jae-dong Lee, Young-rae Park, Ho-Young Kim
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Publication number: 20050014330Abstract: A method of planarizing an interlayer dielectric layer formed over a one cylinder storage (OCS) capacitor including applying two or three interlayer dielectric layers over the capacitor and planarizing the interlayer dielectric layers using CMP having a different etching selectivity according to the layers.Type: ApplicationFiled: February 12, 2004Publication date: January 20, 2005Inventors: Young-Rae Park, Jae-Dong Lee, Joon Park, Chang-Ki Hong
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Publication number: 20040132223Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.Type: ApplicationFiled: October 17, 2003Publication date: July 8, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-heon Park, Chang-ki Hong, Jae-dong Lee, Young-rae Park, Ho-Young Kim
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Patent number: 6716732Abstract: A method of fabricating a contact pad of a semiconductor device is disclosed. The method includes forming a stopping layer over the semiconductor substrate. An interdielectric layer is formed over the stopping layer, and the interdielectric layer is planarized to expose at least a gate upper dielectric layer by using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer. The interdielectric layer is etched in a region in which a contact pad will be formed on the semiconductor substrate. A conductive material is deposited on the semiconductor substrate. Finally, planarizing is carried out using a material which exhibits a high-polishing selectivity of the upper dielectric layer with respect to the conductive material.Type: GrantFiled: November 8, 2001Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Young-rae Park, Jung-yup Kim, Bo-un Yoon, Sang-rok Hah
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Patent number: 6695684Abstract: A chemical mechanical polishing apparatus includes a polishing pad on which a wafer requiring planarization is placed, a conditioning disc having an abrasive surface for conditioning the polishing pad, a tank containing de-ionized water in which the conditioning disc soaks while standing by, and a cleaner for cleaning the conditioning disc. The conditioning disc cleaner is disposed in the tank of de-ionized water to remove polishing impurities from an abrasive surface of the conditioning disc. The cleaner may include a brush having bristles against which the abrasive surface of the conditioning disc is placed when it is lowered into the tank. In operation, after the wafer is polished, an abrasive surface of the conditioning disc is run over the upper surface of the polishing pad to condition the surface of the polishing pad. Then the conditioning disc is moved off of the upper surface of the polishing pad and to a stand-by position in which the abrasive surface of the disc is submerged in a liquid.Type: GrantFiled: October 4, 2001Date of Patent: February 24, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Young-rae Park, Ho-young Kim, Hong-kyu Hwang
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Publication number: 20040033693Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.Type: ApplicationFiled: August 12, 2003Publication date: February 19, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Rae Park, Jung-Yup Kim, Bo-Un Yoon, Kwang-Bok Kim, Jae-Phil Boo, Jong-Won Lee, Sang-Rok Hah, Kyung-Hyun Kim, Chang-Ki Hong
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Patent number: 6626968Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.Type: GrantFiled: May 21, 2001Date of Patent: September 30, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Young-rae Park, Jung-yup Kim, Bo-un Yoon, Kwang-bok Kim, Jae-phil Boo, Jong-won Lee, Sang-rok Hah, Kyung-hyun Kim, Chang-ki Hong
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Patent number: 6585570Abstract: In method and apparatus for supplying a slurry for a chemical mechanical polishing (CMP) process, a slurry pre-treatment is provided for minimizing the size of abrasive particles in the slurry. In the slurry supplying method, after applying acoustic energy to the slurry to de-agglomerate agglomerated abrasive particles within the slurry, any remaining oversized abrasive particles having a diameter greater than a reference size are filtered out from the slurry. The acoustic energy application step and the filtering step are repeatedly performed for a predetermined time period while circulating the slurry.Type: GrantFiled: May 3, 2001Date of Patent: July 1, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-yup Kim, Young-rae Park, Sang-rok Hah
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Patent number: 6548388Abstract: A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.Type: GrantFiled: March 14, 2001Date of Patent: April 15, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-kyu Hwang, Young-Rae Park, Jung-yup Kim, Jeong-sic Jeon, Bo-un Yoon, Sang-rok Hah
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Patent number: 6518157Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.Type: GrantFiled: July 27, 2001Date of Patent: February 11, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Gee-won Nam, Gi-jong Park, Hong-kyu Hwang, Jun-shik Bae, Young-rae Park, Jung-yup Kim, Bo-un Yoon, Sang-rok Hah
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Patent number: 6498102Abstract: A chemical mechanical polishing (CMP) process employs a ceria-based slurry as an abrasive. In particular, a nitride pattern is formed over a semiconductor substrate, and an oxide layer is then formed over the semiconductor substrate and the nitride pattern. Next, a sacrificial insulation layer which is devoid of surface steps is formed over the oxide layer. The sacrificial insulation layer and the oxide layer are then polished by CMP using the ceria-based slurry and using the nitride pattern as a stopper.Type: GrantFiled: March 12, 2001Date of Patent: December 24, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-yup Kim, Young-rae Park, Sang-rok Hah