Abstract: A semiconductor device may include a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; and a second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command.

Abstract: A semiconductor apparatus includes a clock path, a command path, a delay monitoring circuit, and an output control circuit. The clock path generates a delay clock signal by delaying a clock signal. The command path generates an output command signal from on one of a command signal and the clock signal, based on a monitoring signal. The delay monitoring circuit generates a delay control signal and a latency control signal based on a phase difference between the delay clock signal and the output command signal, when the monitoring signal is enabled. The output control circuit generates an output enable signal by synchronizing the output command signal with the delay clock signal, based on the latency control signal.

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: A semiconductor device may include a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; and a second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command.

Abstract: A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.

Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.

Abstract: A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: An integrated circuit includes: a first differential buffer suitable for receiving a primary signal through a primary input terminal thereof, and receiving a secondary signal through a secondary input terminal thereof, wherein the secondary signal has a phase opposite to a phase of the primary signal; a second differential buffer suitable for receiving a first reference voltage through primary and secondary input terminals thereof; and an operational amplifier suitable for receiving a first common mode voltage of the primary and secondary output terminals of the first differential buffer and a second common mode voltage of the primary and secondary output terminals of the second differential buffer, to output the first reference voltage.

Abstract: An integrated circuit includes: a first differential buffer suitable for receiving a primary signal through a primary input terminal thereof, and receiving a secondary signal through a secondary input terminal thereof, wherein the secondary signal has a phase opposite to a phase of the primary signal; a second differential buffer suitable for receiving a first reference voltage through primary and secondary input terminals thereof; and an operational amplifier suitable for receiving a first common mode voltage of the primary and secondary output terminals of the first differential buffer and a second common mode voltage of the primary and secondary output terminals of the second differential buffer, to output the first reference voltage.

Abstract: A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A delay control device and method are disclosed, which relate to a technology for compensating for a delay difference of a delay locked loop (DLL). The delay control device may include a delay locked loop (DLL) configured to adjust a delay time of a delay line, and compensate for a delay time of a replica delay circuit based on a calibration signal. The delay control device may include a real clock path delay circuit configured to delay an output of the delay locked loop (DLL. The delay control device may include a control signal generator configured to generate the calibration signal in consideration of a difference between the delay time of the replica delay circuit and the delay time of the real clock path delay circuit.

Abstract: A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.

Abstract: A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.