Patents by Inventor Young-way Teh

Young-way Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8853796
    Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: October 7, 2014
    Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.
    Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
  • Patent number: 8664717
    Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Young Way Teh, Vara Vakada
  • Patent number: 8624329
    Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
  • Patent number: 8563394
    Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: October 22, 2013
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
  • Patent number: 8519445
    Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: August 27, 2013
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
  • Publication number: 20130175617
    Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang Liu, Young Way Teh, Vara Vakada
  • Patent number: 8461009
    Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 11, 2013
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Atul C. Ajmera, Christopher V. Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh
  • Publication number: 20120292719
    Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Young Way TEH, Michael V. AQUILINO, Arifuzzaman (Arif) SHEIKH, Yun Ling TAN, Hao ZHANG, Deleep R. NAIR, Jinghong H. (John) LI
  • Publication number: 20120256268
    Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Applicants: GlobalFoundries, Inc., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
  • Patent number: 8106462
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Publication number: 20110266628
    Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Vincent HO, Wenhe LIN, Young Way TEH, Yong Kong SIEW, Bei Chao ZHANG, Fan ZHANG, Haifeng SHENG, Juan Boon TAN
  • Patent number: 7999325
    Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 16, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, John Sudijono, Hui Peng Koh, Liang Choo Hsia
  • Patent number: 7993997
    Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: August 9, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
  • Publication number: 20110169096
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Patent number: 7977185
    Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: July 12, 2011
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
  • Patent number: 7883953
    Abstract: A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Voon-Yew Thean, Christopher V. Baiocco, Jie Chen, Weipeng Li, Young Way Teh, Jin Wallner
  • Patent number: 7867835
    Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: January 11, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jae Gon Lee, Elgin Kiok Boone Quek, Young Way Teh, Wenzhi Gao
  • Patent number: 7785950
    Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 31, 2010
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd, Chartered Semiconductor Manufacturing Ltd
    Inventors: Sunfei Fang, Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh
  • Patent number: 7759206
    Abstract: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: July 20, 2010
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Zhijiong Luo, Young Way Teh, Atul C. Ajmera
  • Publication number: 20100078687
    Abstract: A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Da Zhang, Voon-Yew Thean, Christopher V. Baiocco, Jie Chen, Weipeng Li, Young Way Teh, Jin Wallner