Patents by Inventor Young-way Teh
Young-way Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100078687Abstract: A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Da Zhang, Voon-Yew Thean, Christopher V. Baiocco, Jie Chen, Weipeng Li, Young Way Teh, Jin Wallner
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Publication number: 20100059831Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.Type: ApplicationFiled: November 6, 2009Publication date: March 11, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
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Publication number: 20090315115Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.Type: ApplicationFiled: June 23, 2008Publication date: December 24, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Beichao Zhang, Johnny Widodo, Juan Boon Tan, Yong Kong Siew, Fan Zhang, Haifeng Sheng, Wenhe Lin, Young Way Teh, Jinping Liu, Vincent Ho, Liang Choo Hsia
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Patent number: 7615427Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.Type: GrantFiled: June 5, 2006Date of Patent: November 10, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
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Publication number: 20090218636Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Jae Gon Lee, Elgin Kiok Boone Quek, Young Way Teh, Wenzhi Gao
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Patent number: 7531401Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.Type: GrantFiled: February 8, 2007Date of Patent: May 12, 2009Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.Inventors: Christopher Vincent Baiocco, Xiangdong Chen, Wenzhi Gao, Young Gun Ko, Young Way Teh
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Publication number: 20090085122Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
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Publication number: 20090026549Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.Type: ApplicationFiled: September 30, 2008Publication date: January 29, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Young Way TEH, Yong Meng LEE, Chung Woh LAI, Wenhe LIN, Khee Yong LIM, Wee Leng TAN, John SUDIJONO, Hui Peng KOH, Liang Choo HSIA
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Publication number: 20080315317Abstract: A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Khee Yong Lim, Young Way Teh, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang-Choo Hsia
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Patent number: 7445978Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.Type: GrantFiled: May 4, 2005Date of Patent: November 4, 2008Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, John Sudijono, Hui Peng Koh, Liang Choo Hsia
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Publication number: 20080191284Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., SAMSUNG ELECTRONICS CO., LTD.Inventors: Christopher Vincent Baiocco, Xiangdong Chen, Wenzhi Gao, Young Gun Ko, Young Way Teh
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Publication number: 20080142897Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Young Way Teh, Xiangdong Chen, Jamin F. Fen, Jun Jung Kim, Daewon Yang, Roman Knoefler, Michael P. Belyansky
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Publication number: 20080044967Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer on the wafer, protecting a portion of the stress formation layer, and irradiating the wafer for modification of a stress value of an unprotected portion of the stress formation layer.Type: ApplicationFiled: August 19, 2006Publication date: February 21, 2008Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., SAMSUNG, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Young Way Teh, Johnny Widodo, Jae Eun Park, Michael P. Belyansky
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Patent number: 7307320Abstract: Integrated circuit field effect transistors include a substrate, an isolation region in the substrate that defines an active region in the substrate, spaced apart source/drain regions in the active region, a channel region in the active region between the spaced apart source/drain regions and an insulated gate on the channel region. A differential mechanical stress-producing region is configured to produce different mechanical stress in the channel region adjacent the isolation region compared to remote from the isolation region. The differential mechanical stress-producing region may be formed using patterned stress management films, patterned stress-changing implants and/or patterned silicide films, and can reduce undesired comer effects. Related fabrication methods also are described.Type: GrantFiled: November 7, 2005Date of Patent: December 11, 2007Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd.Inventors: Min-Chul Sun, Young Way Teh
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Publication number: 20070281410Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.Type: ApplicationFiled: June 5, 2006Publication date: December 6, 2007Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
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Patent number: 7297584Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.Type: GrantFiled: October 7, 2005Date of Patent: November 20, 2007Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.Inventors: Jae-Eon Park, Ja-Hum Ku, Jun-Jung Kim, Dae-Kwon Kang, Young Way Teh
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Publication number: 20070202654Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Christopher Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh
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Patent number: 7256084Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.Type: GrantFiled: May 4, 2005Date of Patent: August 14, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang Choo Hsia, Young Way Teh, John Sudijono, Wee Leng Tan, Hui Peng Koh
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Publication number: 20070161244Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.Type: ApplicationFiled: November 22, 2005Publication date: July 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
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Patent number: 6815823Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.Type: GrantFiled: October 6, 2003Date of Patent: November 9, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Young-Way Teh, Victor Seng Keong Lim, Ting Cheong Ang