Abstract: A transistor includes a wire formed on a substrate, the wire comprising a semiconductor core, a first cover enclosing a portion of the semiconductor core, and a second cover enclosing the first cover, a first electrode formed on the second cover of the wire, an insulating layer formed on the first electrode and having contact holes exposing portions the semiconductor core, and a second electrode and a third electrode connected to the wire through the contact holes.

Abstract: A method for efficiently stress testing a service oriented architecture based application. A business process flow is recorded between a client and a server. When an XML document is extracted from the recorded business process flow, an XML document file is created for the extracted XML document, an XML document descriptor file is created comprising XPath queries for data elements in the XML document file, a configuration file is created comprising user input parameters obtained from the recorded business process flow, and test input data file is created. The user input parameters in the configuration file are used to generate a test script to test the service oriented architecture based application, wherein data values from the test input data file are inserted into a template of the XML document file at locations specified by the XPath queries in the XML document descriptor file. The test script is then executed.

Abstract: A display device includes a gate line delivering a gate on/off voltage, a data line insulated to the gate line, a pixel transistor including a gate electrode connected to the gate line, a drain electrode connected to the data line and a source electrode spaced apart with the drain electrode, a pixel electrode connected to the source electrode, a dummy gate line delivering a kick-back compensation voltage complimentary to the gate on/off voltage, and a compensation capacitance formed between a dummy gate electrode connected to the dummy gate line and a dummy source electrode connected to the pixel electrode.

Abstract: A bridge for heterogeneous QoS networks is provided. The bridge comprises an UPnP QoS processing unit, a bridge function unit and at least two of network drive drivers. The UPnP QoS processing unit collects connection information connected through the networks and QoS requirement information thereof through an UPnP QoS structure. The bridge function unit establishes and releases connection by allocating resources based on the collected connection information and QoS requirement information, and performs a bridging operation according to connection information of a received frame. At least two of network device drivers are physically connected to the networks.

Abstract: A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.

Abstract: Provided are an apparatus and a method for injecting liquid crystal into a hollow optic fiber. The apparatus includes: a first holder and a second holder each of which has a fluid passage for holding corresponding one end of the hollow optic fiber to be communicated with the fluid passage a container connected to a tube disposed with a valve at the fluid passage of the second holder and storing liquid crystal; an air supplying device connected to the first holder and the container through tubes having a plurality of valves to select an air passage for making the hollow optic fiber vacuous by sucking air out of the hollow optic fiber and forcedly injecting liquid crystal into the hollow optic fiber by supplying an air pressure.

Abstract: A display apparatus includes a substrate including a display area having a transmissive region and a reflective region and a peripheral area surrounding the display area, a gate line and a data line formed on the substrate and crossing each other to define a pixel area in the display area, a gate electrode and a common electrode, wherein the gate electrode branches from the gate line in the pixel area and the common electrode is spaced apart from the gate electrode, a source electrode and a drain electrode formed on the gate electrode, wherein the source electrode branches from the data line and the drain electrode is spaced apart from the source electrode, and a reflective electrode formed in the pixel area by extending the drain electrode into the pixel area and provided with at least one opening to define the transmissive region and the reflective region.

Abstract: A thin film transistor array panel includes a substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line contacting the semiconductor layer, a drain electrode contacting the semiconductor layer and separated from the data line, a pixel electrode disposed on the gate insulating layer and contacting the drain electrode, a passivation layer disposed on the pixel electrode, and a common electrode disposed on the passivation layer and including a unit electrode overlapping the pixel electrode.

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract: A transistor includes a wire formed on a substrate, the wire comprising a semiconductor core, a first cover enclosing a portion of the semiconductor core, and a second cover enclosing the first cover, a first electrode formed on the second cover of the wire, an insulating layer formed on the first electrode and having contact holes exposing portions the semiconductor core, and a second electrode and a third electrode connected to the wire through the contact holes.

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract: Method and apparatus for displaying information of data to be deleted in a digital video recorder are configured to read management information (e.g., recording date and time) of data to be deleted from a hard disk (HDD) when it is required to overwrite data on the HDD. Data overwriting can occur because of insufficient spare space of the HDD, during the recording operation of a digital video recorder. The read management information can be displayed along with the recording status of the HDD. Accordingly, a user can recognize, in advance, the data to be deleted in accordance with the data overwriting operation, and thus, selectively back up the data to be deleted.

Abstract: Disclosed is a color CRT (Cathode Ray Tube) integrated with deflection circuit. The color CRT includes a sync signal separation and deflection circuit board attached on at least a portion of the color CRT. The sync signal separation and deflection circuit board includes a sync signal separation circuit for separating sync signal from video signal to regenerate video signal into the same contents, a horizontal deflection circuit for impressing horizontal deflection current onto a horizontal deflection coil and a vertical deflection circuit for impressing vertical deflection current onto a vertical deflection coil. The color CRT, which has the sync signal separation and deflection circuit attached on at least a portion of the color CRT, allows a one-to-one matching of the deflection circuit and a deflection yoke by removing the causes of DY fluctuation due to the change of set condition.

Abstract: Disclosed is a color CRT (Cathode Ray Tube) integrated with deflection circuit. The color CRT includes a sync signal separation and deflection circuit board attached on at least a portion of the color CRT. The sync signal separation and deflection circuit board includes a sync signal separation circuit for separating sync signal from video signal to regenerate video signal into the same contents, a horizontal deflection circuit for impressing horizontal deflection current onto a horizontal deflection coil and a vertical deflection circuit for impressing vertical deflection current onto a vertical deflection coil. The color CRT, which has the sync signal separation and deflection circuit attached on at least a portion of the color CRT, allows a one-to-one matching of the deflection circuit and a deflection yoke by removing the causes of DY fluctuation due to the change of set condition.