Abstract: An apparatus for controlling a discharge pressure of a fluid includes: a pump configured to suck the fluid through an inlet or to discharge the sucked fluid through an outlet; a distributor connected to the pump and to an injection nozzle provided by a sensor and configured to distribute the fluid discharged from the pump to the sensor; and a controller. The controller is configured to control the pump to operate selectively in accordance with detection of contamination of the sensor and to control operation of the distributor to be forcibly delayed during operation of the pump such that the fluid distributed to the sensor, when detected as being contaminated, is controlled to reach a selected required discharge pressure of different required discharge pressures selected in accordance with water amount information and a degree of contamination of the sensor.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A method includes switching a vehicle to a 4WD state by connecting a disconnector, maintaining the disconnector in the connected state for a predetermined maintenance time, determining whether a condition to be switched to a 2WD state is satisfied when the predetermined maintenance time period elapses, and disconnecting the disconnector when the condition to be switched to the 2WD state is satisfied.

Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A method includes switching a vehicle to a 4WD state by connecting a disconnector, maintaining the disconnector in the connected state for a predetermined maintenance time, determining whether a condition to be switched to a 2WD state is satisfied when the predetermined maintenance time period elapses, and disconnecting the disconnector when the condition to be switched to the 2WD state is satisfied.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: An exemplary embodiment provides an intruder detection method capable of accurately detecting an intruder and estimating an abnormal behavior of the intruder even when viewpoints of acquired images are different from each other. An intruder detection method is suitable for being performed by an intruder detection device for detecting an intruder based on images and includes: receiving input images acquired by multiple cameras; extracting feature maps associated with a plurality of viewpoints by applying the input images to a plurality of convolutional neural networks provided separately for the plurality of viewpoints of the images; and detecting the intruder based on the feature maps associated with the plurality of viewpoints.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A heater for an evaporator includes a heating wire and a support, and the heating wire includes a tunnel part that surrounds an outer surface of a container in which an organic material is accommodated and is coiled in a cylindrical shape, a flange part that is connected to an upper end of the tunnel part and has a spiral structure in which a radius increases in a plane direction, a first straight part extending downward from a lower end of the tunnel part, and a second straight part extending downward from a distal end of the flange part, and the support includes a ring part that supports a lower surface of the flange part, and a plurality of bars extending downward form the ring part.

Abstract: A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween. At least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction is formed. A buried layer that fills the spaces between the plurality of first patterns while the at least one support structure contacts the upper surface of the pattern structure is formed. The at least one support structure is separated from the pattern structure.

Abstract: A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween. At least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction is formed. A buried layer that fills the spaces between the plurality of first patterns while the at least one support structure contacts the upper surface of the pattern structure is formed. The at least one support structure is separated from the pattern structure.

Abstract: Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: A semiconductor device includes a substrate including a cell array region having a first active region and a peripheral circuit region having a second active region, an insulating layer pattern on the substrate and including a hole corresponding with the first active region, a DC conductive pattern in the hole, connected to the first active region, and buried in the substrate, a bit line connected to the DC conductive pattern and including a first bit line conductive pattern contacting the DC conductive pattern and covering a top surface of the insulating layer pattern, and a gate insulating layer and a gate electrode structure on the second active region, the gate electrode structure including a gate conductive pattern and a first gate electrode conductive pattern, the first gate electrode conductive pattern including a same material as the first bit line conductive pattern.

Abstract: Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: The present invention provides a flexible gas barrier film including: a transparent base film; and a hydrophobic pattern layer formed on the base film. The flexible gas barrier film is capable of maximizing hydrophobicity and effectively reducing water vapor permeability by patterning the hydrophobic layer.

Abstract: A layer deposition method includes: feeding a reactant with a first flow of an inert gas as a carrier gas into a reaction chamber to chemisorb the reactant on a substrate; feeding the first flow of the inert gas to purge the reaction chamber and a first reactant feed line; and feeding the second flow of the inert gas into the reaction chamber through a feed line different from the first reactant feed line.

Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.