Patents by Inventor Young Suk MOON
Young Suk MOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240084437Abstract: A laminate can comprise an oxide disposed over a first major surface of a substrate. The oxide layer can comprise a thickness of about 40 nanometers or less. The oxide layer can comprise oxygen and a first element. The first element can comprise at least one of titanium, tantalum, silicon, or aluminum. The oxide layer can comprise an atomic ratio of oxygen to the another element of about 1.5 or less. The laminate can comprise a peel strength between the substrate and the oxide layer of about 1.3 Newtons per centimeter or more. Methods of making a laminate can comprise providing a substrate comprising a first major surface and depositing an oxide layer over the first major surface of the substrate by sputtering from an elemental target comprising an another element in an oxygen environment.Type: ApplicationFiled: February 9, 2022Publication date: March 14, 2024Inventors: Young Suk Lee, Hyung Soo Moon, Seong-ho Seok
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Patent number: 11449745Abstract: Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.Type: GrantFiled: June 9, 2017Date of Patent: September 20, 2022Assignee: SK hynix Inc.Inventors: Young-Jae Jin, Young-Suk Moon, Hong-Sik Kim
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Patent number: 11221965Abstract: In a cache memory used for communication between a host and a memory, the cache memory may include a plurality of cache sets, each comprising: a valid bit; N dirty bits; a tag; and N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host, wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.Type: GrantFiled: February 27, 2019Date of Patent: January 11, 2022Assignee: SK hynix Inc.Inventors: Seung-Gyu Jeong, Dong-Gun Kim, Jung-Hyun Kwon, Young-Suk Moon
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Patent number: 10990322Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.Type: GrantFiled: May 24, 2019Date of Patent: April 27, 2021Assignee: SK hynix Inc.Inventors: Young-Suk Moon, Hong-Sik Kim
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Patent number: 10860518Abstract: An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.Type: GrantFiled: March 15, 2019Date of Patent: December 8, 2020Assignee: SK hynix Inc.Inventors: Hong-Sik Kim, Young-Suk Moon
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Publication number: 20200026664Abstract: In a cache memory used for communication between a host and a memory, the cache memory may include a plurality of cache sets, each comprising: a valid bit; N dirty bits; a tag; and N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host, wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.Type: ApplicationFiled: February 27, 2019Publication date: January 23, 2020Inventors: Seung-Gyu JEONG, Dong-Gun KIM, Jung-Hyun KWON, Young-Suk MOON
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Patent number: 10482930Abstract: In an embodiment a memory chip may be provided. The memory chip may include a chip select buffer configured to receive a chip select signal, a command buffer configured to receive a command signal, wherein the command signal is input after a time has elapsed since the chip select signal is activated and the command buffer is turned on when the command signal is input.Type: GrantFiled: March 20, 2018Date of Patent: November 19, 2019Assignee: SK hynix Inc.Inventor: Young-Suk Moon
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Publication number: 20190278522Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Applicant: SK hynix Inc.Inventors: Young-Suk MOON, Hong-Sik KIM
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Publication number: 20190213162Abstract: An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Inventors: Hong-Sik KIM, Young-Suk MOON
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Patent number: 10346090Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.Type: GrantFiled: October 7, 2016Date of Patent: July 9, 2019Assignee: SK hynix Inc.Inventors: Young-Suk Moon, Hong-Sik Kim
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Patent number: 10275385Abstract: An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.Type: GrantFiled: February 24, 2017Date of Patent: April 30, 2019Assignee: SK hynix Inc.Inventors: Hong-Sik Kim, Young-Suk Moon
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Publication number: 20190088290Abstract: In an embodiment a memory chip may be provided. The memory chip may include a chip select buffer configured to receive a chip select signal, a command buffer configured to receive a command signal, wherein the command signal is input after a time has elapsed since the chip select signal is activated and the command buffer is turned on when the command signal is input.Type: ApplicationFiled: March 20, 2018Publication date: March 21, 2019Applicant: SK hynix Inc.Inventor: Young-Suk MOON
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Patent number: 10157023Abstract: A memory controller includes a plurality of request queues for storing requests transmitted from corresponding host devices among a plurality of host devices, and a token information generation unit for generating information related to the numbers of first and second tokens corresponding to the plurality of respective host devices. The memory controller also includes a request scheduler for selecting repeatedly and sequentially the plurality of request queues, and outputting requests stored in a selected request queue, by using the first and second tokens, wherein the request scheduler outputs one request per one first token and, when first tokens are all consumed, outputs one request per one second token. The scheduler may output requests according to a first-ready first-come first-served (FR-FCFS) rule when using a first token, and output requests according to a first-ready (FR) rule when using a second token. The number of first tokens and second tokens may depend on characteristics of the host devices.Type: GrantFiled: February 24, 2017Date of Patent: December 18, 2018Assignee: SK Hynix Inc.Inventors: Young-Suk Moon, Hong-Sik Kim
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Patent number: 10157148Abstract: A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.Type: GrantFiled: October 13, 2014Date of Patent: December 18, 2018Assignee: SK hynix Inc.Inventors: Young-Suk Moon, Hong-Sik Kim
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Patent number: 10146443Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.Type: GrantFiled: September 28, 2015Date of Patent: December 4, 2018Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Won-Gyu Shin, Jung-Whan Choi, Lee-Sup Kim, Young-Suk Moon, Yong-Kee Kwon
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Publication number: 20180089562Abstract: Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.Type: ApplicationFiled: June 9, 2017Publication date: March 29, 2018Inventors: Young-Jae JIN, Young-Suk MOON, Hong-Sik KIM
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Publication number: 20180004446Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.Type: ApplicationFiled: October 7, 2016Publication date: January 4, 2018Inventors: Young-Suk MOON, Hong-Sik KIM
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Patent number: 9798491Abstract: A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.Type: GrantFiled: December 29, 2015Date of Patent: October 24, 2017Assignee: SK Hynix Inc.Inventors: Kyung-Min Lee, Young-Suk Moon
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Patent number: 9792065Abstract: A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.Type: GrantFiled: October 16, 2015Date of Patent: October 17, 2017Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Won-Gyu Shin, Jung-Whan Choi, Lee-Sup Kim, Young-Suk Moon, Yong-Kee Kwon
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Publication number: 20170249104Abstract: A memory controller includes a plurality of request queues suitable for storing requests transmitted from corresponding host devices among a plurality of host devices; a token information generation unit suitable for generating informations on the numbers of first and second tokens corresponding to the plurality of respective host devices; and a request scheduler suitable for selecting repeatedly and sequentially the plurality of request queues, and outputting requests stored in a selected request queue, by using first and second tokens, wherein the request scheduler outputs one request per one first token and, when first tokens are consumed all, outputs one request per one second token.Type: ApplicationFiled: February 24, 2017Publication date: August 31, 2017Inventors: Young-Suk MOON, Hong-Sik KIM