Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure and a gate-cut structure within the sacrificial gate structure at a location positioned above the isolation material, the gate-cut structure having an upper portion and a lower portion, and forming a replacement gate cavity by removing the sacrificial gate structure and the lower portion of the gate-cut structure. The method further includes forming a final gate structure that includes forming a gate insulation layer of the final gate structure on all exposed surfaces of the upper portion of the gate-cut structure, removing the upper portion of the gate-cut structure, removing the exposed portion of the final gate structure to define a gate-cut opening that separates the final gate structure into the first and second final gate structures, and forming a gate separation structure in the gate-cut opening.

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure and a gate-cut structure within the sacrificial gate structure at a location positioned above the isolation material, the gate-cut structure having an upper portion and a lower portion, and forming a replacement gate cavity by removing the sacrificial gate structure and the lower portion of the gate-cut structure. The method further includes forming a final gate structure that includes forming a gate insulation layer of the final gate structure on all exposed surfaces of the upper portion of the gate-cut structure, removing the upper portion of the gate-cut structure, removing the exposed portion of the final gate structure to define a gate-cut opening that separates the final gate structure into the first and second final gate structures, and forming a gate separation structure in the gate-cut opening.

Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

Abstract: A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.

Abstract: A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

Abstract: A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type electrode(s) and p-type electrode(s), and vertical channel transistors on one or more of the n-type electrode(s) and one or more of the p-type electrode(s); each vertical channel transistor including a vertical channel and a gate electrode wrapped therearound, some of the transistors including pull-up transistors. The semiconductor memory structure further includes a routing gate electrode for each gate electrode, and a shared contact having at least two parts, each part situated over the routing gate electrodes for the pull-up transistors. A unit semiconductor memory cell, the semiconductor memory structure and a corresponding method of forming the memory structure are also provided.

Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.