Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

Abstract: Methods to utilize efficient processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing mandrels separated from each other across two adjacent bit-cells on an upper surface of a dielectric layer on an upper surface of a silicon (Si) layer; forming first spacers on opposite sides of each mandrel; forming second spacers on exposed sides of the first spacers; removing the mandrels; removing exposed sections of the dielectric layer; removing the first and second spacers; forming fin-spacers on opposite sides of remaining sections of the dielectric layer; removing the remaining sections of the dielectric layer; removing exposed sections of the Si layer; and removing the fin-spacers to reveal Si fins.

Abstract: Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second mandrels separated from each other across adjacent cells on a Si layer; forming first and second dummy-spacers and third and fourth dummy-spacers on opposite sides of the first and second mandrels, respectively; removing, through a block-mask, the first and fourth dummy spacers and a portion of the second and third dummy-spacers; forming first spacers on each exposed side of the mandrels and in between the second and third dummy-spacers, forming a merged spacer; removing the mandrels; removing a section of the merged-spacer; forming second spacers on all exposed sides of the first spacers and the merged-spacer; removing the merged-spacer and the first spacers; removing exposed sections of the Si layer through the second spacers; and removing the second spacers to reveal Si fins.

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract: Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract: A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask layer on an upper surface of a silicon-oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask; forming spacers on opposite sides of each mandrel, removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces; removing exposed sections of the hard-mask exposing sections of the silicon-oxide, removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask where the block-mask portions had been; removing the hard-mask through the cut-mask openings, removing the cut-mask; forming cavities in exposed regions of the silicon-oxide; removing the spacers and any remaining hard-mask; and forming metal lines in the cavities.

Abstract: A process for manufacturing integrated circuit devices includes providing a set of original color rules defining an original color rule space and defining a design space. The improvement involves applying a perturbed color rule space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and reconfiguring the router processing engine in accordance with the exposed decomposition errors.

Abstract: In one example, the method includes performing at least one process operation to form a first plurality of active fins and at least one sacrificial fin in a first area of a substrate while forming only a second plurality of active fins in a second area of said substrate, forming a fin removal masking layer that covers all of the active fins in both said first and second areas and exposes said at least one sacrificial fin in the first area, with the fin removal masking layer in position, performing at least one etching process to remove the at least one sacrificial fin in the first area and removing the fin removal masking layer.

Abstract: In one example, the method includes performing at least one process operation to form a first plurality of active fins and at least one sacrificial fin in a first area of a substrate while forming only a second plurality of active fins in a second area of said substrate, forming a fin removal masking layer that covers all of the active fins in both said first and second areas and exposes said at least one sacrificial fin in the first area, with the fin removal masking layer in position, performing at least one etching process to remove the at least one sacrificial fin in the first area and removing the fin removal masking layer.

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.