Patents by Inventor Youri Ponomarev

Youri Ponomarev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959876
    Abstract: A cap for use with devices, such as sensors. The cap includes protrusions on its underside, to restrict the movement of a liquid or a gel placed under cap. The protrusions may take the form of walls or pillars, depending on the application. As such, the cap retains the liquid or gel in a specified position on the device. For example, an electrochemical sensor may require a liquid electrolyte to remain in place over one or more electrodes. The protrusions may not extend far enough to touch the device, but rather leave a small gap. However, because of the surface tension of the liquid, the liquid generally stays within the protrusions.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 16, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Alfonso Berduque, Donal McAuliffe, Brendan Cawley, Raymond J. Speer, Youri Ponomarev
  • Publication number: 20210262973
    Abstract: A cap for use with devices, such as sensors. The cap includes protrusions on its underside, to restrict the movement of a liquid or a gel placed under cap. The protrusions may take the form of walls or pillars, depending on the application. As such, the cap retains the liquid or gel in a specified position on the device. For example, an electrochemical sensor may require a liquid electrolyte to remain in place over one or more electrodes. The protrusions may not extend far enough to touch the device, but rather leave a small gap. However, because of the surface tension of the liquid, the liquid generally stays within the protrusions.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: Alfonso Berduque, Donal McAuliffe, Brendan Cawley, Raymond J. Speer, Youri Ponomarev
  • Patent number: 11022579
    Abstract: A cap for use with devices, such as sensors. The cap includes protrusions on its underside, to restrict the movement of a liquid or a gel placed under cap. The protrusions may take the form of walls or pillars, depending on the application. As such, the cap retains the liquid or gel in a specified position on the device. For example, an electrochemical sensor may require a liquid electrolyte to remain in place over one or more electrodes. The protrusions may not extend far enough to touch the device, but rather leave a small gap. However, because of the surface tension of the liquid, the liquid generally stays within the protrusions.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 1, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Alfonso Berduque, Donal McAuliffe, Brendan Cawley, Raymond J. Speer, Youri Ponomarev
  • Publication number: 20190242847
    Abstract: A cap for use with devices, such as sensors. The cap includes protrusions on its underside, to restrict the movement of a liquid or a gel placed under cap. The protrusions may take the form of walls or pillars, depending on the application. As such, the cap retains the liquid or gel in a specified position on the device. For example, an electrochemical sensor may require a liquid electrolyte to remain in place over one or more electrodes. The protrusions may not extend far enough to touch the device, but rather leave a small gap. However, because of the surface tension of the liquid, the liquid generally stays within the protrusions.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Inventors: Alfonso Berduque, Donal McAuliffe, Brendan Cawley, Raymond J. Speer, Youri Ponomarev
  • Patent number: 9331219
    Abstract: Disclosed is an integrated circuit comprising a substrate having a major surface; a directional light sensor, the directional light sensor comprising a plurality of photodetectors on a region of said major surface, said plurality of photodetectors comprising a set of first photodetectors for detecting light from a first direction and a set of second photodetectors for detecting light from a second direction, wherein a first photodetector is located adjacent to a second photodetector; and a light blocking structure comprising a first portion extending from said major surface in between the first photodetector and the second photodetector; and a second portion extending from the first portion and at least partially overhanging at least one of the first photodetector and the second photodetector. A device including such an IC and a method of manufacturing such an IC are also disclosed.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 3, 2016
    Assignee: NXP, B.V.
    Inventors: Zoran Zivkovic, Youri Ponomarev
  • Publication number: 20150171231
    Abstract: Disclosed is an integrated circuit comprising a substrate having a major surface; a directional light sensor, the directional light sensor comprising a plurality of photodetectors on a region of said major surface, said plurality of photodetectors comprising a set of first photodetectors for detecting light from a first direction and a set of second photodetectors for detecting light from a second direction, wherein a first photodetector is located adjacent to a second photodetector; and a light blocking structure comprising a first portion extending from said major surface in between the first photodetector and the second photodetector; and a second portion extending from the first portion and at least partially overhanging at least one of the first photodetector and the second photodetector. A device including such an IC and a method of manufacturing such an IC are also disclosed.
    Type: Application
    Filed: May 2, 2013
    Publication date: June 18, 2015
    Inventors: Zoran Zivkovic, Youri Ponomarev
  • Patent number: 8233957
    Abstract: A sensor module (130) for a catheter (110), the sensor module (130) comprising a biofilm detection unit (131) adapted for detecting a characteristic of a biofilm (132) and electric circuitry (135, 800) for providing an output signal indicative of a result of the detection.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: July 31, 2012
    Assignee: NXP B.V.
    Inventors: Matthias Merz, Youri Ponomarev, Remco Pijnenburg
  • Publication number: 20110301903
    Abstract: A sensor, electrically connected to transponder, is calibrated in an environment of operational use of the transponder. The calibrating uses as a reference a value of a parameter representative of the environment.
    Type: Application
    Filed: April 30, 2009
    Publication date: December 8, 2011
    Applicant: NXP B.V.
    Inventors: Arelie Humbert, Gilbert Curatola, Matthias Merz, Remco Henricus Wilhelmus Pijenburg, Romano Hoofman, Youri Ponomarev
  • Patent number: 7951684
    Abstract: A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6?), wherein the material of the insulating layers (6,6?) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: May 31, 2011
    Assignee: NXP B.V.
    Inventor: Youri Ponomarev
  • Publication number: 20110018097
    Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) including a plurality of circuit elements and a metallization stack (20) covering said substrate for providing interconnections between the circuit elements, wherein the top metallization layer of said stack carries a plurality of metal portions (30) embedded in an exposed porous material (40) for retaining a liquid, said porous material laterally separating said plurality of metal portions. An electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 27, 2011
    Applicant: NXP B.V.
    Inventors: Youri Ponomarev, Aurelie Humbert, Roel Daamen
  • Patent number: 7838367
    Abstract: The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20) being executed from the first side of the semiconductor body (2) through and on both sides of the first gate electrode (7), which implantation results in a change of property of the silicon below the first gate electrode (7) compared to the silicon on both sides of the gate electrode 7) in a section of the channel region (5) remote from the first gate dielectric (6A), and on the second surface of the semiconductor body (2) a cavity (30) being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (6B,8) is deposited in the cavity thus formed.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: November 23, 2010
    Assignee: NXP B.V.
    Inventors: Youri Ponomarev, Josine Loo
  • Patent number: 7829411
    Abstract: The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: doping the first and the second semiconductor region with a different dopant concentration, and oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500° C. and 700° C., preferably between 500° C. and 650° C. A corresponding device is also provided. Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rate increase.
    Type: Grant
    Filed: January 20, 2003
    Date of Patent: November 9, 2010
    Assignee: NXP B.V.
    Inventors: Josine Johanna Gerarda Petra Loo, Youri Ponomarev, Robertus Theodorus Fransiscus Schaijk
  • Publication number: 20100264492
    Abstract: A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions (38, 40), activated source and drain regions (30, 32) and a body region (34). The structure may be a double gated SOI structure or a fully depleted (FD) SOI structure. A sharp intergace and low resistance are achieved with a process that uses spacers (28) and which fully replaces the full thickness of a semiconductor layer with the contact regions.
    Type: Application
    Filed: June 6, 2006
    Publication date: October 21, 2010
    Inventors: Radu Surdeanu, Gerben Doornbos, Youri Ponomarev, Josine Loo
  • Patent number: 7772646
    Abstract: There is a method of manufacturing a semiconductor device with a semiconductor body comprising a semiconductor substrate and a semiconductor region which are separated from each other with an electrically insulating layer which includes a first and a second sub-layer which, viewed in projection, are adjacent to one another, wherein the first sub-layer has a smaller thickness than the second sub-layer, and wherein, in a first sub-region of the semiconductor region lying above the first sub-layer, at least one digital semiconductor element is formed and, in a second sub-region of the semiconductor region lying above the second sub-layer, at least one analog semiconductor element is formed. According to an example embodiment, the second sub-layer is formed in that the lower border thereof is recessed in the semiconductor body in relation to the lower border of the first sub-layer Fully depleted SOI devices are thus formed.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: August 10, 2010
    Assignee: NXP B.V.
    Inventors: Josine Johanna Gerarda Petra Loo, Vincent Charles Venezia, Youri Ponomarev
  • Publication number: 20100010327
    Abstract: A sensor module (130) for a catheter (110), the sensor module (130) comprising a biofilm detection unit (131) adapted for detecting a characteristic of a biofilm (132) and electric circuitry (135, 800) for providing an output signal indicative of a result of the detection.
    Type: Application
    Filed: January 11, 2008
    Publication date: January 14, 2010
    Applicant: NXP, B.V.
    Inventors: Matthias Merz, Youri Ponomarev, Remco Pijnenburg
  • Publication number: 20100010550
    Abstract: An implantable medical system for electrical recording and or providing therapy to a plurality of tissue sites without damage to surrounding blood vessels is disclosed comprising: an implant body having a plurality of therapy elements, the elements being hingedly attached at one end to the surface of the body and releasably extendable outward from the surface of the body at the other end; a release mechanism for each of the elements; and a coating material covering the body and the elements; wherein upon dissolution of the coating material after implantation, the release mechanism is capable of causing the elements to extend outward at one end from the surface of the body and into a plurality of tissue sites without damage to the surrounding blood vessels. The method of implanting the system into a body is also disclosed.
    Type: Application
    Filed: September 20, 2007
    Publication date: January 14, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Youri Ponomarev, Matthias Merz, Remco Henricus Wilhelmus Pijnenburg
  • Publication number: 20090209067
    Abstract: A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6?), wherein the material of the insulating layers (6,6?) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.
    Type: Application
    Filed: April 24, 2009
    Publication date: August 20, 2009
    Applicant: NXP B.V.
    Inventor: Youri PONOMAREV
  • Publication number: 20090166799
    Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising a semiconductor substrate (2) and a semiconductor region (3) which are separated from each other by means of an electrically insulating layer (4) which comprises a first and second sublayer (4A, 4B) that are viewed in projection adjacent to each other, whereby the first sublayer (4A) is provided with a smaller thickness than the second sublayer (4B) and whereby in a first subregion (3B) of the semiconductor region (3) lying above the first sublayer (4A) at least one digital semiconductor element (5) is formed and in a second subregion (3B) of the semiconductor region (3) lying above the second sublayer (4B) at least one analogue semiconductor element (6) is formed. According to the invention the second sublayer (4B) is formed in such a way that the lower border thereof is in relation to the lower border of the first sublayer (4A) formed sunken in the semiconductor body (1).
    Type: Application
    Filed: August 10, 2005
    Publication date: July 2, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Josine Johanna Gerarda Petra Loo, Vincent Charles Venezia, Youri Ponomarev
  • Patent number: 7535015
    Abstract: Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant. In a field effect transistor (FET) the quantum wells function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with molecular beam epitaxy (MBE).
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: May 19, 2009
    Assignee: NXP B.V.
    Inventor: Youri Ponomarev
  • Patent number: 7521323
    Abstract: The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: April 21, 2009
    Assignee: NXP B.V.
    Inventors: Radu Catalin Surdeanu, Youri Ponomarev