Abstract: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9).

Abstract: An apparatus and method for improving electrical contact between an implanted device (10) for recording or stimulating neuronal activity and surrounding tissue (12) (e.g., brain tissue, nerve fibers, etc.). In an exemplary embodiment, a nanometer sized topographic structure (36, 136) (e.g., a nanometer scale pillar) is processed for electrical connection with a corresponding electrode (30, 32) of the implanted device (10). The nanometer scale topographic structure (36, 136) bridges a gap (26) between the implanted device (10) and surrounding tissue (12), thus improving neuron-electrode coupling therebetween. The present disclosure can also be extended to any application where capacitive coupling to single or multiple cells (20) can be used for sensing and/or stimulation thereof.

Abstract: Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due to the epitaxial growth, wherein the substrate (1) is a Silicon-On-Insulator substrate with a support layer (1), a buried silicon dioxide layer (BOX) and a monocrystalline Si surface layer (3), the method further including: ion implantation of the Si surface layer (3) and the epitaxial SiGe layer (4) to transform the Si surface layer (3) into an amorphous Si layer (3B) and a portion of the epitaxial SiGe layer (4) into an amorphous SiGe layer (5), a further portion of the epitaxial SiGe layer (4) being a remaining monocrystalline SiGe layer (6), the amorphous Si layer (3B), the amorphous SiGe layer and the remaining monocrystalline SiGe layer (6) forming a layer stack (3B, 5, 6) on the buried silicon dioxide layer (BOX), with the amorphous Si layer

Abstract: An apparatus and method for electrostimulation treatment of neurological diseases is disclosed herein. The apparatus and method include an array (22) of sub-micron (and sub-cell size) FET electrodes (24) that are capacitively coupled to nervous system elements (both neurons (50) and axons (66)) as a replacement for traditional metal shanks in both single- and multi-electrode(s) electrostimulation implantable devices. By using such an approach, significant improvements in selectivity, power consumption and biocompatibility can be achieved, as well as relying on mainstream IC manufacture techniques for the manufacture thereof, making it cost-effective. The present disclosure can also be extended to any application where capacitive coupling to single or multiple cells can be used for sensing and/or stimulation thereof.

Abstract: A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

Abstract: The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20) being executed from the first side of the semiconductor body (2) through and on both sides of the first gate electrode (7), which implantation results in a change of property of the silicon below the first gate electrode (7) compared to the silicon on both sides of the gate electrode (7) in a section of the channel region (5) remote from the first gate dielectric (6A), and on the second surface of the semiconductor body (2) a cavity (30) being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (6B,8) is deposited in the cavity thus formed.

Abstract: A method of fabricating a dual-gate semiconductor device is provided in which wsilicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

Abstract: The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.

Abstract: Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due to the epitaxial growth, wherein the substrate (1) is a Silicon-On-Insulator substrate with a support layer (1), a buried silicon dioxide layer (BOX) and a monocrystalline Si surface layer (3), the method further including: ion implantation of the Si surface layer (3) and the epitaxial SiGe layer (4) to transform the Si surface layer (3) into an amorphous Si layer (3B) and a portion of the epitaxial SiGe layer (4) into an amorphous SiGe layer (5), a further portion of the epitaxial SiGe layer (4) being a remaining monocrystalline SiGe layer (6), the amorphous Si layer (3B), the amorphous SiGe layer and the remaining monocrystalline SiGe layer (6) forming a layer stack (3B, 5, 6) on the buried silicon dioxide layer (BOX), with the amorphous Si layer

Abstract: Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant. In a field effect transistor (FET) the quantum wells function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with molecular beam epitaxy (MBE).

Abstract: A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Abstract: A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.

Abstract: The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: doping the first and the second semiconductor region with a different dopant concentration, and oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500° C. and 700° C., preferably between 500° C. and 650° C. A corresponding device is also provided. Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rate increase.

Abstract: A piezoelectric ceramic composition firable at a reduced sintering temperature is provided. The main composition is expressed with the general formula: [(Pb1-m-n-pSrmBanCdp)(ZrxTi1-x)1-k(BiaMnb)k]O3+yBi2O3+z(Fluorine Compound) where 0.00?m<0.15, 0.00?n<0.15, 0.00<(m+n)<0.21, 0.00 <p<0.04, 0.50?x?0.56, 0.00<a?1.00, 0.00<b?1.00, 0.00<k<0.04, 0.00?y?1.00(in weight %), 0.00?z?1.00(in weight %) and fluorine compound is LiF or MgF2. The ceramic material of the invention can be advantageously used in multilayered piezoelectric ceramic devices, in piezoelectric ceramic transformers, in piezoelectric ceramic actuators or in piezoelectric ceramic transducers.

Abstract: A piezoelectric ceramic composition firable at a reduced sintering temperature is provided.

Abstract: The semiconductor device has a semiconductor body (1) having a field effect transistor (4) at a first surface (2) and a second gate (10) at a second surface (3). The second gate is present in a recess (11) in the semiconductor body (1) which is accurately aligned with a first gate (8) of the field effect transistor (4) on the first surface (2). The method of manufacturing the semiconductor device comprises the step of implanting ions into a semiconductor body (1) which has a first gate (8) on a first surface (2) and a silicon oxide layer (17) on a second surface (3). The implantation is done from the first surface (2) in a direction substantially perpendicular to that surface. The implantation has the effect that behind the first gate (8) an implanted region (18) is formed in the semiconductor body (1) and a circumferential implanted zone (19) in the silicon oxide layer (17). Silicon oxide is formed in the implanted region (18) by dopant-enhanced oxidation.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the semiconductor body (1) by a gate dielectric (26), a structure is provided on the surface (2) comprising a dielectric layer (14) having a recess (16), which recess (16) is aligned to a source zone (11,9) and a drain zone (12,9) of a second conductivity type provided at the surface (2) of the semiconductor body (1) and has side walls (17) extending substantially perpendicularly to the surface (2) of the semiconductor body (1).

Abstract: A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium (6) and a third semiconductor layer of monocrystalline silicon (7) are successively provided on a surface (2) of a silicon wafer (1) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.

Abstract: The semiconductor device has a semiconductor body (1) having a field effect transistor (4) at a first surface (2) and a second gate (10) at a second surface (3). The second gate is present in a recess (11) in the semiconductor body (1) which is accurately aligned with a first gate (8) of the field effect transistor (4) on the first surface (2). The method of manufacturing the semiconductor device comprises the step of implanting ions into a semiconductor body (1) which has a first gate (8) on a first surface (2) and a silicon oxide layer (17) on a second surface (3). The implantation is done from the first surface (2) in a direction substantially perpendicular to that surface. The implantation has the effect that behind the first gate (8) an implanted region (18) is formed in the semiconductor body (1) and a circumferential implanted zone (19) in the silicon oxide layer (17). Silicon oxide is formed in the implanted region (18) by dopant-enhanced oxidation.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the semiconductor body (1) by a gate dielectric (26), a structure is provided on the surface (2) comprising a dielectric layer (14) having a recess (16), which recess (16) is aligned to a source zone (11,9) and a drain zone (12,9) of a second conductivity type provided at the surface (2) of the semiconductor body (1) and has side walls (17) extending substantially perpendicularly to the surface (2) of the semiconductor body (1).