Patents by Inventor Yousuke Hagiwara

Yousuke Hagiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295742
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yousuke HAGIWARA, Kenta SHIBASAKI, Yumi TAKADA
  • Publication number: 20200185044
    Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.
    Type: Application
    Filed: August 30, 2019
    Publication date: June 11, 2020
    Inventors: Yumi TAKADA, Yasuhiro HIRASHIMA, Kenta SHIBASAKI, Yousuke HAGIWARA
  • Patent number: 10644913
    Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 5, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yousuke Hagiwara, Shigehito Saigusa, Mitsuyuki Ashida, Yuki Fujimura, Ichiro Seto
  • Patent number: 10419136
    Abstract: According to an embodiment, a communication device includes a phase-shifting circuit that shifts a phase of a local signal and supplies it to an orthogonal demodulator. The phase-shifting circuit includes first and second signal input ends that are supplied with an output signal of a local oscillator between both ends thereof, a frequency divider that has first and second input ends, and a switching part that is provided between the first and second signal input ends and the first and second input ends of the frequency divider and switches connection between the first and second signal input ends and the first and second input ends of the frequency divider.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 17, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Hagiwara, Yuki Fujimura, Hiroyuki Kobayashi, Ichiro Seto, Shigehito Saigusa
  • Publication number: 20190158325
    Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: Yousuke Hagiwara, Shigehito Saigusa, Mitsuyuki Ashida, Yuki Fujimura, Ichiro Seto
  • Publication number: 20190097851
    Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.
    Type: Application
    Filed: February 21, 2018
    Publication date: March 28, 2019
    Inventors: Yousuke Hagiwara, Shigehito Saigusa, Mitsuyuki Ashida, Yuki Fujimura, Ichiro Seto
  • Patent number: 10225118
    Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: March 5, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yousuke Hagiwara, Shigehito Saigusa, Mitsuyuki Ashida, Yuki Fujimura, Ichiro Seto
  • Patent number: 10069670
    Abstract: A transmission and reception circuit includes a transmission circuit, a reception circuit, and a signal feedback path. The transmission path includes an output section, a signal generating circuit generating an in-phase component signal and an orthogonal component signal, and a transmission analog baseband circuit configured to perform digital to analog conversion of the generated in-phase component signal and orthogonal component signal. The reception circuit includes an input section, a reception analog baseband circuit performing analog to digital conversion of the transmitted in-phase component signal and orthogonal component signal, and a signal detection circuit that detects the analog-to-digital converted in-phase component signal and orthogonal component signal converted by the reception analog baseband circuit.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehito Saigusa, Yousuke Hagiwara, Toshiyuki Yamagishi, Hiroshi Yoshida, Ichiro Seto
  • Publication number: 20180183531
    Abstract: According to an embodiment, a communication device includes a phase-shifting circuit that shifts a phase of a local signal and supplies it to an orthogonal demodulator. The phase-shifting circuit includes first and second signal input ends that are supplied with an output signal of a local oscillator between both ends thereof, a frequency divider that has first and second input ends, and a switching part that is provided between the first and second signal input ends and the first and second input ends of the frequency divider and switches connection between the first and second signal input ends and the first and second input ends of the frequency divider.
    Type: Application
    Filed: September 11, 2017
    Publication date: June 28, 2018
    Inventors: Yousuke Hagiwara, Yuki Fujimura, Hiroyuki Kobayashi, Ichiro Seto, Shigehito Saigusa
  • Patent number: 9954627
    Abstract: A quadrature demodulator includes a quadrature demodulating circuit configured to generate an analog in-phase signal and an analog quadrature signal based on an output signal of a low noise amplifier, and a controller configured to cause a thermal noise, instead of the output signal of the low noise amplifier, to be input to the quadrature demodulating circuit, when a correction parameter to correct a mismatch between the in-phase and quadrature signals is being calibrated.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Hagiwara, Toshiyuki Yamagishi, Toshiya Mitomo
  • Publication number: 20180083823
    Abstract: A transmission and reception circuit includes a transmission circuit, a reception circuit, and a signal feedback path. The transmission path includes an output section, a signal generating circuit generating an in-phase component signal and an orthogonal component signal, and a transmission analog baseband circuit configured to perform digital to analog conversion of the generated in-phase component signal and orthogonal component signal. The reception circuit includes an input section, a reception analog baseband circuit performing analog to digital conversion of the transmitted in-phase component signal and orthogonal component signal, and a signal detection circuit that detects the analog-to-digital converted in-phase component signal and orthogonal component signal converted by the reception analog baseband circuit.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 22, 2018
    Inventors: Shigehito SAIGUSA, Yousuke HAGIWARA, Toshiyuki YAMAGISHI, Hiroshi YOSHIDA, Ichiro SETO
  • Publication number: 20170070299
    Abstract: A quadrature demodulator includes a quadrature demodulating circuit configured to generate an analog in-phase signal and an analog quadrature signal based on an output signal of a low noise amplifier, and a controller configured to cause a thermal noise, instead of the output signal of the low noise amplifier, to be input to the quadrature demodulating circuit, when a correction parameter to correct a mismatch between the in-phase and quadrature signals is being calibrated.
    Type: Application
    Filed: July 18, 2016
    Publication date: March 9, 2017
    Inventors: Yousuke HAGIWARA, Toshiyuki YAMAGISHI, Toshiya MITOMO
  • Publication number: 20160065199
    Abstract: An amplitude detector includes a first amplitude detection transistor and an output terminal. The first amplitude detection transistor receives a first signal by a gate and a second signal that forms a differential pair with the first signal by a drain, and detects an amplitude of the differential pair. The output terminal outputs an amplitude signal in accordance with amplitude detected by the first amplitude detection transistor.
    Type: Application
    Filed: March 1, 2015
    Publication date: March 3, 2016
    Inventor: Yousuke HAGIWARA
  • Patent number: 8849219
    Abstract: In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n?1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Deguchi, Shouhei Kousai, Yousuke Hagiwara, Masamichi Suzuki, Atsuhiro Kinoshita, Takao Marukame
  • Publication number: 20130252559
    Abstract: In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n?1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun DEGUCHI, Shouhei Kousai, Yousuke Hagiwara, Masamichi Suzuki, Atsuhiro Kinoshita, Takao Marukame
  • Patent number: 7969237
    Abstract: A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Yousuke Hagiwara
  • Publication number: 20100259316
    Abstract: A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    Type: Application
    Filed: November 23, 2009
    Publication date: October 14, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Fujita, Yousuke Hagiwara