Patents by Inventor Yu-An Lien

Yu-An Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a semiconductor device having modified profile metal gate
    Patent number: 10418456
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Methods for Controlling an End-to-End Distance in Semiconductor Device
    Publication number: 20190259613
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Source/drain structure having multi-facet surfaces
    Patent number: 10367094
    Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Winnie Chen
  • Structures and methods for fabricating semiconductor devices using fin structures
    Patent number: 10354998
    Abstract: Devices are described herein that include a first fin structure formed on a substrate. A second fin structure formed on the substrate. One or more gate structures are formed on the first fin structure and the second fin structure. A first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. A fin-end source/drain region is associated with a second volume larger than the first volume, the first fin structure being disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Yung-Ta Li, Chun-Hsiang Fan, Tung-Ying Lee, Clement Hsing-Jen Wann
  • Structure of S/D Contact and Method of Making Same
    Publication number: 20190181267
    Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 13, 2019
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chun-Hsiang Fan
  • Methods for controlling an end-to-end distance in semiconductor device
    Patent number: 10312089
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Huan-Just Lin, Huang-Ming Chen, Yang-Cheng Wu, Cheng-Hua Yang
  • Asymmetric source/drain epitaxy
    Patent number: 10312145
    Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • BASE STATION AND USER EQUIPMENT
    Publication number: 20190166581
    Abstract: A base station and a user equipment are provided. The base station performs a multi-user non-orthogonal uplink multiplexing transmission configuration procedure to generate an uplink multiplexing transmission configuration message based on a radio resource utilization efficiency. The uplink multiplexing transmission configuration message carries a power domain uplink multiplexing transmission parameter and a non-orthogonal uplink multiplexing transmission parameter. The base station transmits the uplink multiplexing transmission configuration message to the user equipment to make the user equipment transmit an uplink data signal to the base station according to the uplink multiplexing transmission configuration message.
    Type: Application
    Filed: December 8, 2017
    Publication date: May 30, 2019
    Inventors: Shao-Yu LIEN, Chun-Che CHIEN
  • METHODS FOR CONTROLLING AN END-TO-END DISTANCE IN SEMICONDUCTOR DEVICE
    Publication number: 20190164759
    Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
    Type: Application
    Filed: March 16, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien HUANG, Tsai-Chun LI, Huan-Just LIN, Huang-Ming CHEN, Yang-Cheng WU, Cheng-Hua YANG
  • ASYMMETRIC SOURCE AND DRAIN STRUCTURES IN SEMICONDUCTOR DEVICES
    Publication number: 20190165171
    Abstract: The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien HUANG, Peng Wang
  • FinFETs with Low Source/Drain Contact Resistance
    Publication number: 20190148525
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • FETs and Methods for Forming the Same
    Publication number: 20190148555
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    Publication number: 20190148524
    Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yi-Chen LO, Yu-Lien HUANG, Li-Te LIN
  • Selective Film Growth for Bottom-Up Gap Filling
    Publication number: 20190109004
    Abstract: A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: Yu-Lien Huang, De-Wei Yu
  • Copper etchant solution additives and method for producing copper etchant solution
    Patent number: 10246783
    Abstract: The present disclosure discloses a copper etchant solution additives and a method for producing copper etchant solution. The method includes: producing copper etchant solution additives, wherein the copper etchant solution additives is an inorganic solution with cupric ions (Cu2+), and deionized water is a solvent for the copper etchant solution additives and is electric neutrality; before wet-etching, the copper etchant solution additives is added in the copper etchant solution, and the copper etchant solution is with a cupric ions (Cu2+) concentration of 700-1000 ppm. Through the above method, the present disclosure can improve etchant property of copper etchant solution to increase etching rate and uniformity.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 2, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Yue Wu, Yu-lien Chou, Zhichao Zhou
  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20190097039
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Yu-Lien HUANG, Meng-Chun CHANG
  • Systems and Methods of Presenting Appropriate Actions for Responding to a Visitor to a Smart Home Environment
    Publication number: 20190089934
    Abstract: A method of presenting appropriate actions for responding to a visitor to a smart home environment via an electronic greeting system of the smart home environment, including detecting a visitor of the smart home environment; obtaining context information from the smart home environment regarding the visitor; based on the context information, identifying a plurality of appropriate actions available to a user of a client device for interacting with the visitor via the electronic greeting system; and causing the identified actions to be presented to the user of the client device.
    Type: Application
    Filed: November 10, 2017
    Publication date: March 21, 2019
    Inventors: JASON EVANS GOULDEN, RENGARAJAN ARAVAMUDHAN, Haerim Jeong, Michael Dixon, James Edward Stewart, Sayed Yusef Shafi, Sahana Mysore, Seungho Yang, Yu-An Lien, Christopher Charles Burns, Rajeev Nongpiur, Jeffrey Boyd
  • Systems and Methods of Detecting and Responding to a Visitor to a Smart Home Environment
    Publication number: 20190087646
    Abstract: A method of detecting and responding to a visitor to a smart home environment via an electronic greeting system of the smart home environment, including determining that a visitor is approaching an entryway of the smart home environment; initiating a facial recognition operation while the visitor is approaching the entryway; initiating an observation window in response to the determination that a visitor is approaching the entryway; obtaining context information from one or more sensors of the smart home environment during the observation window; and at the end of the time window, initiating a response to the detected approach of the visitor based on the context information and/or an outcome of the facial recognition operation.
    Type: Application
    Filed: November 10, 2017
    Publication date: March 21, 2019
    Inventors: JASON EVANS GOULDEN, RENGARAJAN ARAVAMUDHAN, Haerim Jeong, Michael Dixon, James Edward Stewart, Sayed Yusef Shafi, Sahana Mysore, Seungho Yang, Yu-An Lien, Christopher Charles Burns, Rajeev Nongpiur, Jeffrey Boyd
  • METHOD, TRANSMITTING NODE AND RECEIVING NODE FOR FEEDBACK CONTROL OF SIDELINK COMMUNICATION
    Publication number: 20190053204
    Abstract: A method, a transmitting node and a receiving node for feedback control of sidelink communication are provided. In the method, the base station generates a target information for transmitting feedback information with respect to data transmissions between a transmitting node and a receiving node; and at least one of the transmitting node and the receiving node receives the target information transmitted by the base station, or receives, from another node, target information transmitted by the base station to the another node; and in response to the transmitting node transmitting the data to the receiving node, the receiving node transmits the feedback information according to the target information, and the transmitting node obtains the feedback information according to the target information.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 14, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Shao-Yu Lien, Hua-Lung Tsai, Chorng-Ren Sheu
  • Structure of S/D contact and method of making same
    Patent number: 10199502
    Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chun-Hsiang Fan