Patents by Inventor Yu-An Lien

Yu-An Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective film growth for bottom-up gap filling
    Patent number: 10170305
    Abstract: A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, De-Wei Yu
  • FinFET thermal protection methods and related structures
    Patent number: 10170332
    Abstract: A method and structure for protecting high-mobility materials from exposure to high temperature processes includes providing a substrate having at least one fin extending therefrom. The at least one fin includes a dummy channel and source/drain regions. A dummy gate stack is formed over the dummy channel. A first inter-layer dielectric (ILD) layer is formed on the substrate including the fin. The first ILD layer is planarized to expose the dummy gate stack. After planarizing the first ILD layer, the dummy gate stack and the dummy channel are removed to form a recess, and a high-mobility material channel region is formed in the recess. After forming the high-mobility material channel region, contact openings are formed within a second ILD layer overlying the source/drain regions, and a low Schottky barrier height (SBH) material is formed over the source/drain regions.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Semiconductor device and a method for fabricating the same
    Patent number: 10164106
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Meng-Chun Chang
  • Method of fabricating a semiconductor device
    Patent number: 10164067
    Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chen Lo, Li-Te Lin, Yu-Lien Huang
  • FETs and methods for forming the same
    Patent number: 10164116
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • FinFETs with low source/drain contact resistance
    Patent number: 10164064
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • USER EQUIPMENT AND BASE STATION
    Publication number: 20180368136
    Abstract: A user equipment (UE) and a base station (BS) are provided. The UE receives an uplink transmission configuration message indicating a pre-configured radio resource pool and an uplink control configuration message indicating an uplink control radio resource in the pre-configured radio resource pool from the BS. The UE transmits an uplink control message on the uplink control radio resource and transmits an uplink data signal on an uplink data radio resource in the pre-configured radio resource pool so that the BS receives the uplink data signal according to the uplink control message.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 20, 2018
    Inventors: Shao-Yu LIEN, Chun-Che CHIEN
  • Method of forming a semiconductor device with multiple etch stop layers and inter-layer dielectrics
    Patent number: 10158020
    Abstract: An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD having a curved top surface. The semiconductor device further comprises a second ESL on the first ILD, the second ESL having a curved top surface, and a second ILD on the second ESL.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Yu-Lien Huang
  • Semiconductor device and fabrication method thereof
    Patent number: 10134897
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Zhao-Cheng Chen
  • FETS and methods of forming FETS
    Patent number: 10134638
    Abstract: An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Yu-Lien Huang, You-Ru Lin
  • FinFET Structure with Different Fin Heights and Method for Forming the Same
    Publication number: 20180301339
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 18, 2018
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Asymmetric Source/Drain Epitaxy
    Publication number: 20180286759
    Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
    Type: Application
    Filed: June 1, 2018
    Publication date: October 4, 2018
    Inventor: Yu-Lien Huang
  • Semiconductor device and a method for fabricating the same
    Patent number: 10056407
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsiang-Ku Shen, Yu-Lien Huang, Wilson Huang, Janet Chen, Jeng-Ya David Yeh
  • Gate structure for semiconductor device
    Patent number: 10050149
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Ching-Feng Fu, Ming-Huan Tsai, D. T. Lee, Cheng-Hua Yang, Yi-Chen Lo
  • Method of forming a contact
    Patent number: 10032887
    Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
  • ARRAY SUBSTRATES AND DISPLAY PANELS
    Publication number: 20180203308
    Abstract: The present disclosure relates to an array substrate and a display panel. The array substrate includes a substrate, a patterned middle layer arranged on the substrate, and a pixel electrode layer configured with no patterns being arranged on the patterned middle layer. The pixel electrode layer includes at least one protrusion area and at least one depressed area formed in accordance with the patterned middle layer. The array substrate may effectively resolve the dark-stripe issues.
    Type: Application
    Filed: July 20, 2016
    Publication date: July 19, 2018
    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Zhichao ZHOU, YU-LIEN CHOU, Yue WU
  • Doorbell Camera
    Publication number: 20180191930
    Abstract: This application is directed to a doorbell camera for illuminating and capturing scenes. The doorbell camera includes at least a subset of processors for operating a camera module, an image sensor having a field of view of a scene and configured to capture video of a portion of the scene, one or more infrared (IR) illuminators for providing illumination, a waterproof button assembly, and a microphone and a speaker for enabling a real-time conversation between a visitor located at the doorbell camera and a user of a remote client device. The waterproof button assembly is configured to receive a user press on a button top, block water from entering the electronic device, and display a visual pattern uniformly at a peripheral region of the button assembly using LEDs and light guide component that are disposed under the button top.
    Type: Application
    Filed: September 20, 2017
    Publication date: July 5, 2018
    Inventors: Haerim Jeong, Rengarajan Aravamudhan, Jacobi Grillo, Michael Dixon, Yu-An Lien, Minjung Kim, Etienne Bérubé, Rochus Jacob, Brian Conner, Scott Mullins
  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20180190809
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Application
    Filed: April 12, 2017
    Publication date: July 5, 2018
    Inventors: Yu-Lien HUANG, Meng-Chun CHANG
  • Copper etchant solution additives and method for producing copper etchant solution
    Publication number: 20180171485
    Abstract: The present disclosure discloses a copper etchant solution additives and a method for producing copper etchant solution. The method includes: producing copper etchant solution additives, wherein the copper etchant solution additives is an inorganic solution with cupric ions (Cu2+), and deionized water is a solvent for the copper etchant solution additives and is electric neutrality; before wet-etching, the copper etchant solution additives is added in the copper etchant solution, and the copper etchant solution is with a cupric ions (Cu2+) concentration of 700-1000 ppm. Through the above method, the present disclosure can improve etchant property of copper etchant solution to increase etching rate and uniformity.
    Type: Application
    Filed: July 11, 2016
    Publication date: June 21, 2018
    Applicant: Shenzhen China Star Optoelectronics Technology Co. , Ltd.
    Inventors: Yue WU, Yu-lien CHOU, Zhichao ZHOU
  • METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    Publication number: 20180175171
    Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.
    Type: Application
    Filed: July 7, 2017
    Publication date: June 21, 2018
    Inventors: Yi-Chen LO, Li-Te LIN, Yu-Lien HUANG