Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: Various semiconductor techniques described herein enable reductions in one or more sizes of a fin field-effect transistor (finFET) and/or increasing one or more sizes of a finFET. In various implementations described herein, a material may be used to reduce the one or more x-direction sizes of the finFET by selective deposition while enabling the one or more y-direction sizes of the finFET to be increased or enlarged by etching. The x-direction size of a source or drain of the finFET, the x-direction size of an active region of the finFET, and/or the x-direction size of a polysilicon region of the finFET may be increased by selective deposition of a boron nitride (BxNy), a boron carbide (BxC), a boron oxide (BxOy) (e.g., boric oxide (B2O3), a fluorocarbon (CxFy) polymer, and/or another material.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: This application is directed to a doorbell camera for illuminating and capturing scenes. The doorbell camera includes at least a subset of processors for operating a camera module, an image sensor having a field of view of a scene and configured to capture video of a portion of the scene, one or more infrared (IR) illuminators for providing illumination, a waterproof button assembly, and a microphone and a speaker for enabling a real-time conversation between a visitor located at the doorbell camera and a user of a remote client device. The waterproof button assembly is configured to receive a user press on a button top, block water from entering the electronic device, and display a visual pattern uniformly at a peripheral region of the button assembly using LEDs and light guide component that are disposed under the button top.

Abstract: An interconnection structure includes a first conductive feature disposed in a dielectric material, a first etch stop layer disposed over the dielectric material, a first dielectric layer disposed over the first etch stop layer, and a second conductive feature extending through the first dielectric layer and the first etch stop layer and in electrical contact with the first conductive feature. The first etch stop layer includes a boron-based layer, and an oxygen-rich boron-containing layer in contact with the boron-based layer.

Abstract: Embodiments of the present disclosure relates to a semiconductor device structure, including a first gate dielectric layer having a top surface and a corner surface, wherein a highest point of the top surface of the first gate dielectric layer is at a first elevation. The semiconductor device structure includes a first gate electrode layer having a top surface, wherein a highest point of the top surface of the first gate electrode layer is at a second elevation higher than the first elevation. The semiconductor device structure includes a first dielectric cap layer in contact with the top surface and the corner surface of the first gate dielectric layer. The first dielectric cap layer is also in contact with the top surface of the first gate electrode layer. The semiconductor device structure includes a first gate spacer in contact with the first dielectric cap layer and the first gate dielectric layer.

Abstract: A semiconductor structure includes at least a fin structure, a gate structure over the fin structure, a connecting structure, a first dielectric structure over the gate structure, and a second dielectric structure. The fin structure extends in a first direction, and the gate structure extends in a second direction different from the first direction. The connecting structure is disposed over the fin structure and isolated from the gate structure. The second dielectric structure extends in the first direction. The first dielectric structure and the second dielectric structure include a same material. A top surface of the first dielectric structure and a top surface of the second dielectric structure are substantially aligned with each other.

Abstract: A method of detecting and responding to a visitor to a smart home environment via an electronic greeting system of the smart home environment, including determining that a visitor is approaching an entryway of the smart home environment; initiating a facial recognition operation while the visitor is approaching the entryway; initiating an observation window in response to the determination that a visitor is approaching the entryway; obtaining context information from one or more sensors of the smart home environment during the observation window; and at the end of the time window, initiating a response to the detected approach of the visitor based on the context information and/or an outcome of the facial recognition operation.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: Various semiconductor techniques described herein enable reductions in one or more sizes of a fin field-effect transistor (finFET) and/or increasing one or more sizes of a finFET. In various implementations described herein, a material may be used to reduce the one or more x-direction sizes of the finFET by selective deposition while enabling the one or more y-direction sizes of the finFET to be increased or enlarged by etching. The x-direction size of a source or drain of the finFET, the x-direction size of an active region of the finFET, and/or the x-direction size of a polysilicon region of the finFET may be increased by selective deposition of a boron nitride (BxNy), a boron carbide (BxC), a boron oxide (BxOy) (e.g., boric oxide (B2O3), a fluorocarbon (CxFy) polymer, and/or another material.

Abstract: A method includes forming fins extending over a semiconductor substrate; forming a photoresist structure over the fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends over the fins, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends in a first direction, wherein each bridge region extends between adjacent cut regions in a second direction, wherein the second direction is within 30° of being orthogonal to the first direction; and performing an etching process using the cut mask as an etching mask.

Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

Abstract: A standing training mobile device for carrying a patient to perform active-assisted upright locomotion is provided. The standing training mobile device includes a base, a mobile module, a lifting module, a control module, and a support module. The mobile module and the lifting module are disposed on the base. The control module is disposed on the lifting module and is coupled to the mobile module. The control module includes a manipulation platform and two control assemblies disposed on the manipulation platform for use of the patient. The support module includes a support frame, a first support assembly, a second support assembly, and a third support assembly. The first support assembly, the second support assembly, and the third support assembly are slidably disposed on the support frame respectively. The second support assembly is disposed between the first support assembly and the third support assembly.

Abstract: A method for manufacturing a semiconductor device includes forming a source/drain region on a semiconductor fin. The source/drain region is adjacent to a dummy gate. The method further includes forming a first dielectric layer over the source/drain region and the dummy gate. The first dielectric layer has a dielectric constant of 3.5 or less. The first dielectric layer may include boron nitride or silicon dioxide with Si-CH3 bonds.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.