Patents by Inventor Yu Cai

Yu Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10691540
    Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 23, 2020
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Chenrong Xiong, Yu Cai, Fan Zhang
  • Patent number: 10693067
    Abstract: The present application provides a touch sensor and a fabricating method thereof and a touch display panel, comprising: a substrate, where the substrate includes a plurality of grooves which are strip-shaped and intersected with each other to define a grid shape; a first infiltrating adjustment layer, disposed on an inside wall of the grooves; and a touch electrodes filled in the groove. The first infiltrating adjustment layer is positioned between the groove and the touch electrodes. An infiltration angle between the touch electrodes in solution state and the first infiltrating adjustment layer is ?, an infiltration angle between the touch electrodes in solution state and the substrate is ?, wherein ? is not equal to ?.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: June 23, 2020
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Yu Cai
  • Patent number: 10691536
    Abstract: A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 23, 2020
    Assignee: SK Hynix Inc.
    Inventors: Aman Bhatia, Fan Zhang, Chenrong Xiong, Naveen Kumar, Yu Cai
  • Patent number: 10693496
    Abstract: A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Chenrong Xiong, Yu Cai, Fan Zhang
  • Patent number: 10687367
    Abstract: A method of performing a random access procedure includes randomly selecting a backoff time from within a backoff window ranging from 0 to a specified multiple of a random access preamble unit, waiting until a time initialized with the backoff time expires, and retransmitting a random access preamble.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Bin Liu, Yongbo Zeng, Jian Wang, Guorong Li, Yu Cai
  • Publication number: 20200185040
    Abstract: A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 11, 2020
    Inventors: Aman BHATIA, Chenrong XIONG, Fan ZHANG, Naveen KUMAR, Xuanxuan LU, Yu CAI
  • Patent number: 10680871
    Abstract: Embodiments of the present invention provide an uplink subcarrier spacing indication method, a base station, and a terminal. The base station determines indication information that is used to indicate a first uplink subcarrier spacing supported by the base station, and communicates with the terminal according to the indication information. During the communication, the base station indicates the first uplink subcarrier spacing supported by the base station to the terminal, so that the terminal subsequently determines, based on the first uplink subcarrier spacing, a second uplink subcarrier spacing supported by the terminal; or the base station receives information that is sent by the terminal and that carries a second uplink subcarrier spacing, in other words, receives an indication from the terminal, so as to learn of the second uplink subcarrier spacing supported by the terminal or to be used by the terminal to send an uplink signal.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 9, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yongbo Zeng, Yanliang Sun, Guorong Li, Yu Cai
  • Patent number: 10672497
    Abstract: A method is provided for controlling a storage system, which can include a plurality of memory cells arranged in blocks and a memory controller coupled to the plurality of memory cells for controlling data write and read in the plurality of memory cells. The method includes identifying a block as a good block, if a count of bad pages in the block is zero, identifying the block as a degraded block if the count of bad pages is below a threshold number, and identifying the block as a bad block if the count of bad pages is above or equal to the threshold number. The method includes using good blocks and degraded blocks for read and program operations, and not using the bad blocks.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 2, 2020
    Assignee: SK Hynix Inc.
    Inventors: Yu Cai, Fan Zhang, Naveen Kumar, Aman Bhatia, Chenrong Xiong, Xuanxuan Lu
  • Patent number: 10640474
    Abstract: A family of novel hybrid compounds comprise a hindered phenolic scorch retardant and an allyl isocyanurate cure co-agent. Combining these two functionalities into a single molecule provides a synergy between the allyl isocyanurate and phenolic groups that achieves an improved balance between curing and scorch.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: May 5, 2020
    Assignee: Dow Global Technologies LLC
    Inventors: Wei Li, Yabin Sun, Jeffrey M. Cogen, Yu Cai
  • Patent number: 10644074
    Abstract: A flexible display panel and a flexible display device are provided. The flexible display panel comprises a display region and a non-display region surrounding the display region, wherein the non-display region includes a bonding area; a flexible substrate having a first surface and an opposite second surface; a light-emitting unit formed on the first surface of the flexible substrate; a first protective film formed on the second surface of the flexible substrate and covering the entire second surface of the flexible substrate, wherein the first protective film has a first side facing the flexible substrate and an opposite second side far away from the flexible substrate; and a second protective film formed on the second side of the first protective film. The flexible display panel includes at least one folding area and at least one non-folding area, and the second protective film only covers the at least one non-folding area.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 5, 2020
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Chuanli Leng, Yu Cai
  • Publication number: 20200112989
    Abstract: A terminal communication method includes processing, by a sending terminal, two adjacent signals when a sending interval between the two adjacent signals that are to be sent at discontinuous time intervals is less than a first preset value, where a processing manner includes at least one of adjusting a transmission moment of at least one of the two adjacent signals such that the sending interval between the two adjacent signals is greater than the first preset value, adjusting a transmission moment of at least one of the two adjacent signals such that the two adjacent signals are sent at continuous time intervals, or discarding a retransmitted signal in the two adjacent signals.
    Type: Application
    Filed: January 26, 2017
    Publication date: April 9, 2020
    Inventors: Yongbo Zeng, Yu Cai, Da Wang
  • Publication number: 20200110664
    Abstract: Embodiments of the present disclosure relate to method and apparatus for data protection. For example, there is provided a computer-implemented method. According to the computer-implemented method, it only needs to read the changed data to be protected rather than the entire data to be protected during the procedure of generating a redundant data portion for the changed data to be protected. Thus, I/O and memory consumptions can be reduced.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Ronnie Yu Cai, Ao Sun, Gary Jialei Wu, Lu Lei, Chen Wang
  • Patent number: 10601546
    Abstract: A dynamic interleaver performs a read operation to identify bit lines with high failures, and form groups of data bits for parity bits computation, such that each group includes at most one data bit from the bit lines with high failures. Thus, the interleave selects the bit lines with high failures based on a most recent read test, and can be adjusted according to the conditions of the storage device.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 24, 2020
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yu Cai, Chenrong Xiong, Fan Zhang, Xuanxuan Lu
  • Publication number: 20200090731
    Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 19, 2020
    Inventors: Naveen KUMAR, Yu CAI, Fan ZHANG
  • Publication number: 20200092845
    Abstract: A paging message sending method includes determining, by a first terminal, that a second terminal is paged. The method further includes sending, by the first terminal to the second terminal, a first message. The first message is used to enable the second terminal to determine that the second terminal is paged.
    Type: Application
    Filed: June 9, 2017
    Publication date: March 19, 2020
    Inventors: Yu Cai, Jian Wang, Yongbo Zeng
  • Publication number: 20200081863
    Abstract: An electronic device and a usage method thereof are provided. The electronic device includes a first device, a second device and a control device. The first device includes a first processor and a first control module, and the first control module is electrically connected to the first processor. The second device is detachably disposed on the first device. The second device includes a second processor and a second control module, and the second control module is electrically connected to the second processor. The control device is detachably connected to the second device, and the first device, the second device and the control device are coupled to each other.
    Type: Application
    Filed: July 29, 2019
    Publication date: March 12, 2020
    Inventors: Tzu-Jen Mao, Kuan-Pei Lee, Fu-Yu Cai, Chieh Mii, Ya-Yun Huang, Ming-Chih Huang, Tong-Shen Hsiung, Shang-Chih Liang
  • Publication number: 20200073496
    Abstract: An organic light-emitting display panel and fabrication method thereof are provided. The organic light-emitting display panel includes an organic light-emitting element array substrate, a thin film encapsulation layer covering the organic light-emitting element array substrate, and touch-control electrodes. The thin film encapsulation layer includes at least one inorganic layer and at least one organic layer. First groove structures are configured in at least one organic layer, and sidewalls of the first groove structures are arc-shaped. The touch-control electrodes are disposed in the first groove structures.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Yu CAI, Xuening LIU, Heeyol LEE, Quanpeng YU, Conghui LIU
  • Patent number: 10580514
    Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 3, 2020
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch
  • Publication number: 20200042384
    Abstract: A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.
    Type: Application
    Filed: May 23, 2019
    Publication date: February 6, 2020
    Inventors: Naveen Kumar, Aman Bhatia, Yu Cai, Fan Zhang
  • Publication number: 20200043557
    Abstract: A method is provided for operating a storage system including memory cells and a memory controller. Each memory cell is an m-bit multi-level cell (MLC), where m is an integer. The method includes performing a soft read operation of a target memory cell and determining a current LLR (log likelihood ratio) value based on result from the soft read operation. The method also includes grouping m-bit cell values of neighboring memory cells and the target memory cell to respective n-bit indices, based on effect of neighboring memory cells on the LLR of the target memory cell, wherein n is an integer and n<m. An LLR compensation value is determined based on the n-bit indices, and a compensated LLR value is determined based on the current LLR value and the LLR compensation value. The method also includes performing soft decoding using the compensated LLR value.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 6, 2020
    Inventors: Yu Cai, Jun Feng, Norton Chu, Fan Zhang