Patents by Inventor Yu-Chang Lin

Yu-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190185106
    Abstract: The present disclosure relates to hub apparatuses and associated systems. An embodiment of the hub apparatus includes a rotor assembly, a shaft, and a stator assembly. The rotor assembly includes first/second housing components and multiple magnets mounted on one or both of the first and second housing components. The stator assembly includes (1) a coil assembly positioned corresponding to the magnets; (2) a main circuit board fixedly coupled to the coil assembly; and (3) a battery assembly positioned inside the coil assembly and carried by the main circuit board.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 20, 2019
    Inventors: Shih-Yuan Lin, Yu-Se Liu, Po-Chang Yeh, Liang-Yi Hsu, Chen-Hsin Hsu
  • Publication number: 20190163061
    Abstract: The present invention relates to a polyimide precursor and a lithography pattern formed by the same. The polyimide precursor has a repeating unit having a structure of formula (I): in the formula (I), Ar represents a tetravalent group derivated from a tetracarboxylic dianhydride compound; R1 represents a divalent group derivated from a diamine compound; and R2 independently represent a thermal-crosslinking group, a photosensitive-crosslinking group, or a hydrogen atom. The polyimide precursor has an excellent pattern-forming ability.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 30, 2019
    Inventors: Chi-Shian CHEN, Bin-Ling TSAI, Yu-Pei CHEN, Chiao-Pei CHEN, Yu-Fu LIAO, Shih-Chang LIN, Chen-Ni CHEN, Tsung-Tai HUNG, Chiu-Feng CHEN
  • Publication number: 20190157163
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 23, 2019
    Inventors: YU-CHANG LIN, SHIH-HSIANG CHIU, TIEN-SHUN CHANG, CHUN-FENG NIEH, HUICHENG CHANG
  • Publication number: 20190067458
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Publication number: 20190006363
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Application
    Filed: August 20, 2018
    Publication date: January 3, 2019
    Inventors: Yu-Chang LIN, Chun-Feng NIEH, Huicheng CHANG, Hou-Yu CHEN, Yong-Yan LU
  • Patent number: 10115808
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Tien-Shun Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li
  • Publication number: 20180301417
    Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 18, 2018
    Inventors: Hung-Ming Chen, Yu-Chang Lin, Chung-Ting Li, Jen-Hsiang Lu, Hou-Ju Li, Chih-Pin Tsao
  • Patent number: 10056383
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Publication number: 20180151706
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: June 1, 2017
    Publication date: May 31, 2018
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Tien-Shun Chang, Wei-Ting Chien, Chin-Pin Tsao, Hou-Ju Li
  • Publication number: 20180145177
    Abstract: FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Yu-Chang Lin, Wei-Ting Chien, Chun-Feng Nieh, Wen-Li Chiu, Huicheng Chang, Chun-Sheng Liang
  • Publication number: 20180051451
    Abstract: An activation system for electronic urinal comprises a urinal fluidly communicated with an inlet pipe and a control unit arranged between the urinal and the inlet pipe. The control unit includes a solenoid valve, a sensor, and a power supply. The solenoid valve is used for controlling to water or seal. The sensor is electrically connected to the solenoid valve. The power supply provides power to the solenoid valve and the sensor. The control unit has an activation switch which is electrically connected to the solenoid valve. The activation switch has a wireless transmission module and a timing controller for turning off the wireless transmission module. The activation switch is pressed so that the wireless transmission module is activated to set water discharge and a turn-off time of the solenoid valve and is turned off after a preset time counted by the time controller to save power.
    Type: Application
    Filed: August 18, 2016
    Publication date: February 22, 2018
    Inventors: Hsiang-Hung Wang, Yu-Chang Lin
  • Patent number: 9768044
    Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: D794581
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 15, 2017
    Assignee: TIMOTION TECHNOLOGY CO., LTD
    Inventor: Yu-Chang Lin
  • Patent number: D800076
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 17, 2017
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventors: Yu-Chang Lin, Bing-Sen Zhuang
  • Patent number: D800195
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 17, 2017
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin
  • Patent number: D810164
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: February 13, 2018
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin
  • Patent number: D815167
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: April 10, 2018
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin
  • Patent number: D817279
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 8, 2018
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventors: Yu-Chang Lin, Bing-Sen Zhuang
  • Patent number: D817897
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 15, 2018
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin
  • Patent number: D819100
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 29, 2018
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin