Patents by Inventor Yu Chen Wang
Yu Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9983257Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.Type: GrantFiled: October 15, 2015Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Cheng Wu, Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Ku-Ning Chang, Yu-Chen Wang
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Patent number: 9678829Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.Type: GrantFiled: June 17, 2016Date of Patent: June 13, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
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Publication number: 20170110202Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.Type: ApplicationFiled: October 15, 2015Publication date: April 20, 2017Inventors: Wei Cheng Wu, Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Ku-Ning Chang, Yu-Chen Wang
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Publication number: 20170110201Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.Type: ApplicationFiled: October 15, 2015Publication date: April 20, 2017Inventors: Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Wei Cheng Wu, Ku-Ning Chang, Yu-Chen Wang
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Publication number: 20170060785Abstract: An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus.Type: ApplicationFiled: April 20, 2016Publication date: March 2, 2017Inventors: Kuen Long CHANG, Yu Chen WANG, Ken Hui CHEN
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Patent number: 9514834Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.Type: GrantFiled: September 28, 2015Date of Patent: December 6, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang
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Patent number: 9514088Abstract: A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.Type: GrantFiled: February 11, 2015Date of Patent: December 6, 2016Assignee: Macronix International Co., Ltd.Inventors: Ken Hui Chen, Kuen Long Chang, Yu Chen Wang
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Publication number: 20160292031Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.Type: ApplicationFiled: June 17, 2016Publication date: October 6, 2016Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
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Patent number: 9400712Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.Type: GrantFiled: January 22, 2014Date of Patent: July 26, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
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Publication number: 20160085715Abstract: A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.Type: ApplicationFiled: February 11, 2015Publication date: March 24, 2016Inventors: Ken Hui CHEN, Kuen Long CHANG, Yu Chen WANG
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Publication number: 20160027522Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.Type: ApplicationFiled: September 28, 2015Publication date: January 28, 2016Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: CHUN-HSIUNG HUNG, NAI-PING KUO, KUEN-LONG CHANG, KEN-HUI CHEN, YU-CHEN WANG
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Patent number: 9208842Abstract: A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value.Type: GrantFiled: January 24, 2014Date of Patent: December 8, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Ken-Hui Chen, Kuen-Long Chang, Yu-Chen Wang, Chin-Hung Chang, Chia-Feng Cheng, Min-Hsiung Meng
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Patent number: 9147501Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.Type: GrantFiled: May 28, 2013Date of Patent: September 29, 2015Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang
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Publication number: 20150213864Abstract: A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Ken-Hui Chen, Kuen-Long Chang, Yu-Chen Wang, Chin-Hung Chang, Chia-Feng Cheng, Min-Hsiung Meng
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Patent number: 9093172Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.Type: GrantFiled: April 9, 2014Date of Patent: July 28, 2015Assignee: Macronix International Co., Ltd.Inventors: Nai-Ping Kuo, Su-Chueh Lo, Kuen-Long Chang, Chun-Hsiung Hung, Chia-Feng Cheng, Ken-Hui Chen, Yu-Chen Wang
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Publication number: 20150205666Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: Macronix International Co., Ltd.Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
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Patent number: 8929139Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.Type: GrantFiled: November 30, 2011Date of Patent: January 6, 2015Assignee: Macronix International Co., Ltd.Inventors: Nai-Ping Kuo, Su-Chueh Lo, Kuen-Long Chang, Chun-Hsiung Hung, Chia-Feng Cheng, Ken-Hui Chen, Yu-Chen Wang
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Publication number: 20140281768Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.Type: ApplicationFiled: May 28, 2013Publication date: September 18, 2014Applicant: Macronix International Co., Ltd.Inventors: CHUN-HSIUNG HUNG, NAI-PING KUO, KUEN-LONG CHANG, KEN-HUI CHEN, YU-CHEN WANG
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Publication number: 20140219026Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Nai-Ping Kuo, Su-Chueh Lo, Kuen-Long Chang, Chun-Hsiung Hung, Chia-Feng Cheng, Ken-Hui Chen, Yu-Chen Wang
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Patent number: 8717813Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.Type: GrantFiled: November 30, 2011Date of Patent: May 6, 2014Assignee: Macronix International Co., Ltd.Inventors: Nai-Ping Kuo, Su-Chueh Lo, Kuen-Long Chang, Chun-Hsiung Hung, Chia-Feng Cheng, Ken-Hui Chen, Yu-Chen Wang