Patents by Inventor Yu-Cheng Chen

Yu-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11178895
    Abstract: Provided is a use of a Macaranga tanarius preparation or extract for manufacturing a composition for enhancing immunity of an insect, particularly a bee. Also provided is a method for enhancing immunity of an insect, particularly a bee. The method comprises administering an effective amount of a composition of the present invention to the insect.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: November 23, 2021
    Assignee: NATUREWISE BIOTECH & MEDICALS CORPORATION
    Inventors: Yu-Cheng Kuo, Chung-Yang Huang, Chia-Chung Hou, Chi-Jung Chen
  • Publication number: 20210358825
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 18, 2021
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • Publication number: 20210358816
    Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
  • Publication number: 20210355207
    Abstract: Disclosed herein are method and/or kit for rendering a diagnosis on whether a subject is suffering from peripheral neuropathy pain. The method comprises detecting the presence of advillin in a biological sample by forming an immune complex between advillin and a monoclonal antibody specifically binds thereto. Also disclosed herein is a method of treating a subject suffering from peripheral neuropathy pain.
    Type: Application
    Filed: March 5, 2019
    Publication date: November 18, 2021
    Applicant: Academia Sinica
    Inventors: Chih-Cheng CHEN, Yu-Chia CHUANG
  • Patent number: 11177291
    Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Hiroshi Osawa, Kyung-Wook Kim, Ming-Chin Hung, Shih Chang Chang, Yu-Cheng Chen
  • Patent number: 11171040
    Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
  • Patent number: 11163343
    Abstract: Systems and methods for a flexible Power Supply Unit (PSU) bay are described. In some embodiments, a chassis may include a surface and a PSU adaptor disposed on the surface, the PSU adaptor comprising a tab having a stopper coupled thereto, where the stopper is configured to: (a) resist movement, bending, or deformation of a board perpendicularly disposed with respect to the surface upon insertion of a first PSU into a PSU cage, and (b) move downward upon insertion of a second PSU into the PSU cage.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: November 2, 2021
    Assignee: Dell Products, L.P.
    Inventors: Chun-Cheng Lin, Yu-Lin Chen, Yueh-Chun Tsai, Jen-Chun Hsueh
  • Patent number: 11158509
    Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Patent number: 11159237
    Abstract: A data transmission system is provided in the invention. The data transmission system includes a transmitting device and a receiving device. The transmitting device encodes data into a color pattern, and displays the color pattern. The receiving device extracts the color pattern and decodes the color pattern to obtain the data.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 26, 2021
    Assignee: ACER INCORPORATED
    Inventors: Yen-Shuo Huang, Chih-Wen Huang, Wen-Cheng Hsu, Chao-Kuang Yang, Ling-Fan Tsao, Chueh-Pin Ko, Chih-Chiang Chen, Tai Ju, Yu-Shan Ruan
  • Patent number: 11158555
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ting Kuo, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Chih-Hsuan Tai, Ying-Cheng Tseng
  • Publication number: 20210329099
    Abstract: An electronic apparatus and a data transmission method thereof are provided. The data transmission method is adapted to an electronic apparatus including a screen, and the data transmission method includes the following steps. An image frame is displayed through the screen. A selection marquee is displayed on the image frame through the screen, and the selection marquee is configured for selecting a partial image frame from the image frame. Connection information is displayed within the selection marquee through the screen, and feature information of data to be transmitted is recognized from the partial image frame selected by the selection marquee. A connection with another electronic apparatus is established according to the connection information. The data to be transmitted is sent to the another electronic apparatus via the connection according to the feature information.
    Type: Application
    Filed: September 25, 2020
    Publication date: October 21, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Chieh Huang, Chih-Wen Huang, Wen-Cheng Hsu, Chao-Kuang Yang, Ling-Fan Tsao, Chueh-Pin Ko, Chih-Chiang Chen, Tai Ju, Yu-Shan Ruan
  • Patent number: 11137370
    Abstract: A sensor with a nanowire heater may be provided. The sensor may be patterned in a device layer of a Silicon on Insulation (SOI) wafer comprising a backside layer and a Buried Oxide (BOX) layer and the nanowire heater may be patterned in the device layer of the SOI wafer adjacent to the sensor. Next, metal routing may be created for the SOI wafer and a bond carrier wafer may be provided on a metal routing side of the SOI wafer. The backside layer may then be ground until the BOX layer is exposed. Then the device layer may be patterned through the BOX layer to expose the sensor and the nanowire heater. A dielectric may be deposited covering at least one of the following: the sensor; and the nanowire heater.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Allen Timothy Chang, Tung-Tsun Chen, Jui-Cheng Huang, Yu-Jie Huang, Yi-Hsing Hsiao
  • Patent number: 11139225
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Chih-Hung Hsu, Mei-Lin Hsieh, Yi-Cheng Hsu, Yuan-Chun Chen, Yu-Shun Hsieh, Ko-Pu Wu
  • Patent number: 11133813
    Abstract: An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 28, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jie-Fan Lai, Shih-Hsiung Huang, Yu-Chang Chen, Chih-Lung Chen, Tzu-Hao Hung, Tai-Cheng Lee
  • Publication number: 20210290158
    Abstract: A wearable electronic device with a function of detecting a wearing state, comprising: a plurality of electrodes; a capacitance calculating circuit, coupled to the electrodes, configured to calculate capacitance variations generated by at least two of the electrode; and a wearing state determining circuit, coupled to the capacitance calculating circuit, configured to determine the wearing state according to the capacitance variations. The wearing state determining circuit determines that the user wears the wearable electronic device in a proper manner if the capacitance variations indicate at least two of the electrodes indicate the user touches wearing state determining circuit. By this way, the wearing state can be auto detected and the wearable electronic device can be correspondingly control according to the wearing state.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Che-Chia Hsu, Jian-Cheng Liao, Yu-Han Chen, Chi-Chieh Liao
  • Patent number: 11122260
    Abstract: A method and apparatus of Inter prediction for video coding including IBC (Intra Block Copy) are disclosed. In one method, an IBC Merge candidate list is generated from Merge candidates associated with one or more candidate types, wherein one or more target candidates associated with a target candidate type are excluded from the IBC Merge candidate list when one or more constraints are satisfied. Current motion information associated with the current block is encoded or decoded using the IBC Merge candidate list. According to another method, a pruning process for the IBC Merge candidate list is skipped or simplified according to block width, block height, or block area of the current block.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 14, 2021
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu
  • Patent number: 11119101
    Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 14, 2021
    Inventors: Jui-Cheng Huang, Chin-Hua Wen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Ching-Hui Lin
  • Patent number: 11115653
    Abstract: A method for generating a list of merge candidates for Intra Block Copy (IBC) prediction is provided. A video codec receives data to be encoded or decoded as a current block of a current picture of a video. A plurality of spatially adjacent neighboring blocks of the current block are coded before the current block. The video codec generates a list of merge candidates including intra picture candidates that are associated with motion information referencing pixels in the current picture. The intra picture candidates comprises candidates that are associated with some but not all of the two or more spatially adjacent neighboring blocks of the current block. The video codec selects a merge candidate from the generated list. The video codec encodes or decodes the current block by using the motion information of the selected merge candidate to generate a prediction of the current block.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 7, 2021
    Assignee: MediaTek Inc.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 11107881
    Abstract: The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: August 31, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang, Min Lung Huang, Yu Cheng Chen, Syu-Tang Liu