Abstract: A circuit board structure includes a core, a wiring layer and a buried passive component. The wiring layer and the buried passive component are disposed on the core, and the buried passive component is electrically connected to the wiring layer. The buried passive component includes a first spiral metal layer, a second spiral metal layer and a dielectric interlayer. The first spiral metal layer is intertwined with the second spiral metal layer. The dielectric interlayer is disposed between the first spiral metal layer and the second spiral metal layer. The first spiral metal layer and the second spiral metal layer are spaced apart by the dielectric interlayer at least in the core.

Abstract: An optical fiber connector includes a fastener member threadedly connected to a main housing. A resilient member is received in the main housing and the fastener member, and abuts against the fastener member. A rotatable tube seat is sleeved by the resilient member, and is positioned by the main housing and the resilient member. A turning member is sleeved on the rotatable tube seat, and is sleeved by the fastener member. The rotatable tube seat is co-rotatable with the turning member. When the fastener member is loosened from the main housing, the turning member is rotatable relative to the fastener member to drive rotation of the rotatable tube seat relative to the main housing.

Abstract: A processor comprises an execution unit and a performance switching module coupled to the execution unit. The performance switching module includes a control unit, a clock control unit, a voltage control unit and a multi-cycle path control unit. The control unit is configured to output at least one control instruction according to a performance requirement of the processor. The clock control unit is configured to receive a clock adjustment instruction on the at least one control instruction to adjust a clock rate provided to the execution unit. The voltage control unit is configured to receive a voltage adjustment instruction of the at least one control instruction to adjust a supplied voltage provided to the execution unit. The multi-cycle path control unit is configured to receive a path adjustment instruction of the at least one control instruction to adjust a cycle number of the instruction execution cycle of the execution unit.

Abstract: The present disclosure provides a smart pole charging system and a monitoring method. The database system initiates a configuration according to an original environmental status. The charging module is connected with an electric vehicle and provides the electrical energy to the electric vehicle. The monitoring module monitors a real-time environmental status around corresponding smart pole. The calculating module recognizes the real-time environmental status and outputs a calculation result. The router receives the calculation result. The cloud platform is communicated with the router and the database system. The router transmits the calculation result to the cloud platform through an open charge point protocol.

Abstract: An image encoder includes a tone mapper, an enhancement layer and an image file generator. The tone mapper is used to generate a base image according to an enhanced image and red green blue (RGB) gains. The RGB gains are set close to or the same as each other. The enhancement layer is used to generate a tone curve and/or a gain map of the base image and the enhanced image according to the tone mapper and/or a group including the base image and the enhanced image. The image file generator is used to generate an image file according to the base image and at least one member of a group including the tone curve and the gain map.

Abstract: An illumination system, configured to generate an illumination light beam, is provided. The illumination system includes an excitation light source configured to emit an excitation light beam and a light guide module, a collimation lens group, and a wavelength conversion element disposed on a transmission path of the excitation light beam. After being emitted from the excitation light source, the excitation light beam is reflected by the light guide module, passes through the collimation lens group, and is transmitted to the wavelength conversion element. A part of the excitation light beam is reflected by the wavelength conversion element, and passes through the collimation lens group and the light guide module. Another part of the excitation light beam is converted into a conversion light beam by the wavelength conversion element. The conversion light beam passes through the collimation lens group and the light guide module. A projection device is also provided.

Abstract: An IC structure includes a biologically sensitive field-effect transistor (BioBET) in a semiconductor substrate, and a dielectric layer over a backside surface of the semiconductor substrate. The dielectric layer has a sensing well extending through the dielectric layer to a channel region of the BioFET. The IC structure further includes a biosensing film, a plurality of fluid channel walls, and a first heater. The biosensing film lines the sensing well in the dielectric layer. The fluid channel walls are over the biosensing film and define a fluid containment region over the sensing well of the dielectric layer. The first heater is in the semiconductor substrate. The first heater has at least a portion overlapping with the fluid containment region.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: An optical lens system includes six lens elements from an object side to an image side, the six lens elements are, in order from the object side to the image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The image-side surface of the second lens element is concave in a paraxial region thereof. The third lens element has positive refractive power. The image-side surface of the fourth lens element is concave in a paraxial region thereof. The image-side surface of the sixth lens element includes at least one inflection point.

Abstract: A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.

Abstract: A memory device includes a memory array comprising a plurality of word lines, the plurality of word lines operatively coupled to a plurality of sets of memory cells, respectively. The memory device includes a controller operatively coupled to the memory array, and comprising an adaptive tracking circuit. The adaptive tracking circuit is configured to: receive a first signal conducted through a first tracking line; receive an address signal indicating one of the word lines to be asserted; and adjust, based on the address signal, a timing of a transition edge of a second signal conducted through a second tracking line.

Abstract: A semiconductor structure including a substrate, a capacitor, and an oxide semiconductor field effect transistor (OSFET). The capacitor is located on the substrate. The oxide semiconductor field effect transistor is located on the substrate. The oxide semiconductor field effect transistor is electrically connected to the capacitor.

Abstract: A computing device include a chassis, a mounting ear, a lever, and a locking unit. The chassis holds one or more electronic devices and is insertable into a rack, such as a server rack. The mounting ear is coupled to the chassis. The lever is rotatably coupled to the mounting ear and is rotatable between a first position and a second position. In the first position, the lever engages the rack to prevent the chassis from being removed. In the second position, the lever disengages the rack and allows the chassis to be removed. The locking unit is coupled to the mounting ear and transitions between locked and unlocked states. In the locked state, the locking unit secures the lever in the first position. In the unlocked state, the lever is movable from the first position to the second position.

Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.

Abstract: The present disclosure provides a camera device including a first frame, a second frame, a camera component, and a driving component. The first frame includes a first arc surface on an inner surface of the first frame and recessing inward to form a circular arc shape. The second frame is movably disposed in the first frame and includes a second arc surface on an outer surface of the second frame and protruding outward to form a circular arc shape. The camera component is fixedly disposed in the second frame. The driving component is disposed on the first frame and the second frame, and the driving component is configured to drive the second frame to rotate with the first direction, the second direction, and the third direction as the axes.

Abstract: A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.

Abstract: A computing device collects a plurality of data samples. Each data sample represents a signal activity of a plurality of signals of the chip. The computing device selects a subset of signals from the plurality of signals as proxies. These proxies are correlated with an actual power consumption of the chip according to a criterion. The computing device trains the power model using signal activities of the plurality of signals as inputs and the actual power consumption as an output. The computing device fine-tunes coefficients of the proxies in the power model. This fine-tuning adjusts an estimation error between an estimated power consumption output by the power model and the actual power consumption.

Abstract: A large area deposition type additive manufacturing equipment is disclosed. The large area deposition type additive manufacturing equipment includes a light source module, a dynamic photomask module, a raw material tank and a deposition module. The light source module includes a plurality of light emitting members, a light diffusion member, a light enhancement member and a light emitting angle limiter. Light emitted from the light emitting members passes through the light diffusion member, the light enhancement member and the light emitting angle limiter to become a collimated curing light. The collimated curing light travels through a transparent member of the raw material tank and a dynamic photomask module to reach liquid photocurable material in the raw material tank, thereby curing the liquid photocurable material. The angle of emitted light ranges within ±30° with respect to a normal line of an incident plane of the light source module.

Abstract: A method for forming a die package structure, including disposing a plurality of dies on a carrier substrate, wherein the top surface of each die has a plurality of signal junctions. The method also includes forming a vertical wire on each of the signal junctions, forming a supporting dielectric layer on the carrier substrate, wherein the supporting dielectric layer covers the dies and exposes the top of the vertical wires, and forming a plurality of redistribution traces on the supporting dielectric layer, wherein the redistribution traces are electrically connected to each of the vertical wires. The method further includes forming a bump at the bonding site of each of the redistribution traces, and performing a cutting process to singulate the dies.

Abstract: A non-volatile memory and an operating method thereof are provided. The non-volatile memory includes a memory array and a controller. Each main memory cell string, a first judgment memory cell string, and a second judgment memory cell string of the memory array respectively includes a plurality of main memory cells, a plurality of first judgment memory cells and a plurality of second judgment memory cells. During a programming operation, the controller determines, according to a data level of each main memory cell, a data level of the corresponding first judgment memory cell, determines, according to data levels of each first judgment memory cell and its preceding first judgment memory cell, a data level of the 10 corresponding second judgment memory cell, and accordingly determines whether to perform a pre-programming operation during an erasing operation.