Patents by Inventor Yu-Chiang Cheng

Yu-Chiang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060257664
    Abstract: This invention discloses a manufacturing method and a structure for printed circuit boards. The printed circuit boards are often used for supporting electronic components in circuit and conducting the heat from electronic components. The printed circuit board structure includes a laminated structure. The laminated structure comprises an electric conduction layer and an insulation layer. The electric conduction layer can be made of a special thermal conduction material, including a metal and a bracket structure of carbon element. The insulation layer can be made of thermal conduction material as well, combining a bracket structure of carbon element. The bracket structure of carbon element has high thermal conductivity so as to improve the heat conduction efficiency. The corresponding manufacturing method for this thermal conduction material can be made with chemical vapor deposition, physical vapor deposition, electroplating or the other materials preparation method.
    Type: Application
    Filed: February 24, 2006
    Publication date: November 16, 2006
    Inventors: Ming-Hang Hwang, Yu-Chiang Cheng, Chao-Yi Chen, Hsin-Lung Kuo, Bin-Wei Lee, Wei-Chung Hsiao
  • Publication number: 20060255451
    Abstract: This invention discloses a manufacturing process method and a structure for a heat conduction interface material. This heat conduction interface material is often used as a buffer interface between chips and heat dissipation devices and is conducted the waste heat from the chips. The heat conduction interface material can be combined a plastic material and a bracket structure of carbon element. The corresponding manufacturing process method for this heat conduction interface material comprises a mixed process that is composed of a plastic material and a bracket structure of carbon element. The bracket structure of carbon element has high thermal conductivity, so as to improve the efficiency of heat conduction. The bracket structure of carbon element can be mixed into the metal and resins.
    Type: Application
    Filed: February 24, 2006
    Publication date: November 16, 2006
    Inventors: Ming-Hang Hwang, Yu-Chiang Cheng, Chao-Yi Chen, Hsin-Lung Kuo, Bin-Wei Lee, Wei-Chung Hsiao
  • Publication number: 20060205118
    Abstract: This invention discloses a manufacturing method and a structure for a chip heat dissipation. This heat dissipation structure includes a bottom plate of circuit structure, a die of central processing unit and a cap. The cover is often used in conducting the waste heat generated from the chip. The cover can be made of a special thermal conduction material, including a metal and a bracket structure of carbon element which have high thermal conductivity so as to improve the efficiency of heat conduction. The corresponding manufacturing method for this heat conduction material can be made with chemical vapor deposition, physical vapor deposition, electroplating or the other materials preparation method. The bracket structure of carbon element can be coated on the metal surface and also can be mixed into the metal.
    Type: Application
    Filed: February 17, 2006
    Publication date: September 14, 2006
    Inventors: Ming-Hang Hwang, Yu-Chiang Cheng, Chao-Yi Chen, Ping-Feng Lee, Hsin-Lung Kuo, Bin-Wei Lee, Wei-Chung Hsiao
  • Publication number: 20060071840
    Abstract: A circuit structure for modifying characteristic impedance by using different reference planes is provided. The structure comprises an analog signal line, a digital signal line, a reference plane for analog signals and a reference plane for digital signals. Wherein, the line width of the analog signal line is the same as that of the digital signal line. In addition, the distance between the analog signal line and the analog signal reference plane is longer than the distance between the digital signal line and the digital signal reference plane. Accordingly, the characteristic impedance mismatch during signal transmission can be solved and the quality of signal transmission can be improved.
    Type: Application
    Filed: June 9, 2005
    Publication date: April 6, 2006
    Inventors: Yu-Chiang Cheng, Kuo-Ming Chuang
  • Patent number: 6922049
    Abstract: A testing method is provided for a printed circuit board that includes a board body formed with first and second conductive traces thereon. The first and second conductive traces are configured for transmitting a high-frequency differential signal and have segments parallel to each other. Each of the segments has an inner edge proximate to the segment of the other of the first and second conductive traces, and an outer edge distal from the segment of the other of the first and second conductive traces. Each of a pair of conductive pads formed on the printed circuit board is disposed proximate to and is connected electrically to the outer edge of the segment of a respective one of the first and second conductive traces.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: July 26, 2005
    Assignee: Mitac International Corp.
    Inventors: Yu-Chiang Cheng, Hsueh-Chin Liao
  • Publication number: 20050007717
    Abstract: A circuit for suppressing electromagnetic interference (EMI) and operation method thereof is provided. Interfering signals captured or coupled from the motherboard are transmitted to the phase-shifter for shifting the phase of the signals. The interfering signals with phase shifted are outputted and coupled to the ground layer or the power-supply layer to offset EMI noise thereof. Since merely additional space for the phase shifter is reserved on the motherboard, EMI effect is eliminated and time and cost for rerouting the circuit is thus reduced.
    Type: Application
    Filed: June 23, 2004
    Publication date: January 13, 2005
    Inventors: Kuo-Ming Chuang, Yu-Chiang Cheng
  • Patent number: 6792056
    Abstract: The specification discloses a cancellation circuit that suppresses electromagnetic interference in a high speed circuit using a function generator so as to utilize differential signals to cancel the magnetic field and to couple with the electric field without affecting the quality of signals. The differential signals are generated from a clock pin of the function generator, which is phase shifted by a phase shifter and passes through a microstrip antenna or a stripline antenna so as to emit electromagnetic waves with inversed phases, canceling the originally existent electromagnetic waves.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 14, 2004
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Publication number: 20040150388
    Abstract: A testing method is provided for a printed circuit board that includes a board body formed with first and second conductive traces thereon. The first and second conductive traces are configured for transmitting a high-frequency differential signal and have segments parallel to each other. Each of the segments has an inner edge proximate to the segment of the other of the first and second conductive traces, and an outer edge distal from the segment of the other of the first and second conductive traces. Each of a pair of conductive pads formed on the printed circuit board is disposed proximate to and is connected electrically to the outer edge of the segment of a respective one of the first and second conductive traces.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Applicant: Mitac International Corp
    Inventors: Yu-Chiang Cheng, Hsueh-Chin Liao
  • Publication number: 20040109278
    Abstract: A transformer circuit for a power source having a first voltage level and a second voltage level. The first coil is coupled to the first voltage level at a terminal of the first coil to generate a first induced voltage by a first current. The demagnetization loop switch is coupled between another terminal of the first coil and the second voltage level to switch the first current according to a switching signal provided by an outside circuit. The demagnetization circuit is coupled between another terminal of the first coil and the first voltage level to consume the energy stored in the first coil when the demagnetization loop switch is turned off. The second coil is coupled to the second voltage level at a terminal of the second coil to generate a signal having a second induced voltage according to the first induced voltage.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 10, 2004
    Applicant: MITAC TECHNOLOGY CORP. and MITAC INTERNATIONAL CORP.
    Inventors: Andy Lee, Yu-Chiang Cheng
  • Publication number: 20030131472
    Abstract: In a method of fabricating a multi-layer circuit board assembly, at least two multi-layer circuit board modules are provided. Each of the modules has a lateral edge provided with a plurality of solder pads that are connected electrically with module interconnect circuit traces on a respective one of the modules. The modules are stacked one upon the other, and are bonded together such that the solder pads of one of the modules are connected to registered ones of the solder pads of the other one of the modules, thereby establishing electrical connection among the circuit traces on the modules.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 17, 2003
    Applicant: Mitac international Corp.
    Inventors: Yu-Chiang Cheng, Jong-Kuei Chen
  • Publication number: 20030103340
    Abstract: An EMI cancellation circuit embedded in an IC. The EMI cancellation circuit is placed close to a noise signal source. During the manufacturing process of the IC, the EMI cancellation circuit is packaged into the IC to suppress the EMI generated by the IC.
    Type: Application
    Filed: December 4, 2001
    Publication date: June 5, 2003
    Inventor: Yu-Chiang Cheng
  • Publication number: 20030098177
    Abstract: A multi-layer circuit board includes ground and power metal layers, signal wiring layers, and a plurality of insulating substrates disposed sequentially one above the other. Each adjacent pair of the metal layers and the signal wiring layers are spaced apart by one of the insulating substrates. At least one of the signal wiring layers is suitable for high-speed low-impedance signal transmission, and is separated from the adjacent one of the metal layers by an adjacent one of the insulating substrates, which is made from a first insulator material having a first dielectric coefficient. The other ones of the insulating substrates, that are not adjacent to the high-speed low-impedance signal wiring layers, are made of a second insulator material having a second dielectric coefficient lower than the first dielectric coefficient.
    Type: Application
    Filed: November 26, 2001
    Publication date: May 29, 2003
    Applicant: MITAC INTERNATIONAL CORP.
    Inventor: Yu-Chiang Cheng
  • Patent number: 6548858
    Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.0 mm. Each of the first and fifth insulating substrates has a thickness ranging from 5.225 to 5.775 mil. Each of the second and fourth insulating substrates has a thickness ranging from 7.6 to 8.4 mil. The third insulating substrate has a thickness ranging from 3.8 to 4.2 mil. The first signal wiring layer has a first resistance with respect to the ground wiring layer. The second signal wiring layer has a second resistance with respect to the ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the ground wiring layer and the power wiring layer.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 15, 2003
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Patent number: 6489570
    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates disposed sequentially one above the other; first, second, third and fourth signal wiring layers; first, second and third ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 7.5 mil. Each of the second and sixth insulating substrates has a thickness ranging from 3 to 13 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 15 mil. The fourth insulating substrate has a thickness ranging from 2 to 6 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first and second ground wiring layers. The third signal wiring layer has a third resistance with respect to the third ground wiring layer and the power wiring layer.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: December 3, 2002
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Publication number: 20020153164
    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates disposed sequentially one above the other; first, second, third and fourth signal wiring layers; first, second and third ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 7.5 mil. Each of the second and sixth insulating substrates has a thickness ranging from 3 to 13 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 15 mil. The fourth insulating substrate has a thickness ranging from 2 to 6 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first and second ground wiring layers. The third signal wiring layer has a third resistance with respect to the third ground wiring layer and the power wiring layer.
    Type: Application
    Filed: March 6, 2001
    Publication date: October 24, 2002
    Applicant: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Publication number: 20020153613
    Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.0 mm. Each of the first and fifth insulating substrates has a thickness ranging from 5.225 to 5.775 mil. Each of the second and fourth insulating substrates has a thickness ranging from 7.6 to 8.4 mil. The third insulating substrate has a thickness ranging from 3.8 to 4.2 mil. The first signal wiring layer has a first resistance with respect to the ground wiring layer. The second signal wiring layer has a second resistance with respect to the ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the ground wiring layer and the power wiring layer.
    Type: Application
    Filed: March 6, 2001
    Publication date: October 24, 2002
    Applicant: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Patent number: 6429749
    Abstract: The invention is a cancellation circuit that suppresses electromagnetic interference in a high speed circuit, which achieves the objects of canceling the magnetic field and coupling the electric field through a differential signal under the premise of not affecting the signal quality. The differential signal is generated from the original high speed circuit using a phase shifter. Suitable phase shifters include a same-layer type, a meander type and a different-layer stacking type.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: August 6, 2002
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Patent number: 6417460
    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates; first, second, third, fourth and fifth signal wiring layers; first and second ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 6.5 mil. Each of the second, fourth and sixth insulating substrates has a thickness ranging from 3 to 9 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 23 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the first ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the second ground wiring layer and the power wiring layer.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: July 9, 2002
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Patent number: 6384340
    Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer, and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.2 mm. Each of the first and fifth insulating substrates has a thickness ranging from 4.175 to 4.725 mil. Each of the second and fourth insulating substrates has a thickness ranging from 5.7 to 6.3 mil. The third insulating substrate has a thickness ranging to 16.8 mil.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: May 7, 2002
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Patent number: RE39766
    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates disposed sequentially one above the other; first, second, third and fourth signal wiring layers; first, second and third ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 7.5 mil. Each of the second and sixth insulating substrates has a thickness ranging from 3 to 13 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 15 mil. The fourth insulating substrate has a thickness ranging from 2 to 6 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first and second ground wiring layers. The third signal wiring layer has a third resistance with respect to the third ground wiring layer and the power wiring layer.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: August 14, 2007
    Assignee: Mitac Technology Corp.
    Inventor: Yu-Chiang Cheng