Patents by Inventor Yu-Chih Liu
Yu-Chih Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972956Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.Type: GrantFiled: May 22, 2020Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
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Patent number: 11417643Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: GrantFiled: November 5, 2019Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 11133285Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.Type: GrantFiled: March 21, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 10879140Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.Type: GrantFiled: December 20, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
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Patent number: 10867835Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.Type: GrantFiled: December 17, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
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Publication number: 20200286748Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Inventors: Chin-Liang CHEN, Wei-Ting LIN, Yu-Chih LIU, Kuan-Lin HO, Jason SHEN
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Patent number: 10685853Abstract: A lid attach process includes providing a substrate and a die attached to the substrate, providing a lid and dipping a periphery of the lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid, and positioning the lid over the die and placing the lid on a top of the substrate with the adhesive material being adapted to interface with a periphery of the substrate.Type: GrantFiled: November 2, 2016Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
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Publication number: 20200066704Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: ApplicationFiled: November 5, 2019Publication date: February 27, 2020Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 10515941Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: GrantFiled: December 29, 2017Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Publication number: 20190221544Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20190139817Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
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Publication number: 20190122946Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
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Patent number: 10269763Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.Type: GrantFiled: March 17, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 10269668Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.Type: GrantFiled: June 5, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
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Patent number: 10163754Abstract: Embodiments of a lid covering a device die improving heat dissipation for a die package are described. Trenches are formed on the bottom side of a lid to increase surface area for heat dissipation. Various embodiments of the trenches on the lid are described. The layout and design of the trenches could be optimized to meet the heat dissipation need of the device die(s). By using the lid with trenches, heat dissipation efficiency is improved and the amount of thermal interface material (TIM) could be reduced. In addition, the selection of thermal interface materials for the lid is widened.Type: GrantFiled: December 26, 2013Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Sheng-Hsiang Chiu, Hsin-Yu Pan, Yu-Chih Liu, Chin-Liang Chen
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Patent number: 10157863Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure.Type: GrantFiled: November 6, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Chi-Yang Yu, Yu-Chih Liu
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Patent number: 10157772Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.Type: GrantFiled: August 14, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
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Publication number: 20180122791Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Publication number: 20180061783Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Inventors: Kuan-Lin Ho, Chin-Liang Chen, Chi-Yang Yu, Yu-Chih Liu
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Patent number: 9893043Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip on a first chip, wherein a first interconnect including a support structure and a bonding structure is disposed between the first chip and the second chip; bonding the first chip and the second chip via a thermal process applied to the bonding structure of the first interconnect; stacking a third chip on the second chip, wherein a second interconnect including a support structure and a bonding structure is disposed between the second chip and the third chip; bonding the second chip and the third chip via the thermal process applied to the bonding structure of the second interconnect; and reflowing the bond between the first and second chips and simultaneously reflowing the bond between the second and third chips.Type: GrantFiled: June 6, 2014Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Liang Chen, Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Shih-Yen Lin