Patents by Inventor Yu-Ching Lee

Yu-Ching Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10845342
    Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Publication number: 20200365571
    Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
  • Publication number: 20200357914
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 10833196
    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
  • Publication number: 20200338115
    Abstract: The present disclosure provides a use of pentosan polysulfate sodium (PPS) in the manufacture of a medicament for the prevention of recurrent urinary tract infection (rUTI) in a human subject, comprising a therapeutically effective dosage for oral administration of PPS, wherein the therapeutically effective dosage for oral administration of PPS is 5-1 mg/kg/day.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 29, 2020
    Inventors: YA-CHUN WANG, YU-CHING CHANG, HSIAO TIEN MA, JEN-YAU CHEN, YUAN-JU LEE, EN MENG, SHANG-JEN CHANG
  • Patent number: 10818777
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chen-Feng Hsu, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Publication number: 20200331364
    Abstract: An automotive seat rail includes a rail and an engaging structure. The engaging structure includes a fixing frame, an engaging member and an elastic member. The fixing frame includes a fixing portion and an abutting portion fixed to and abutting an inner rail respectively. The engaging member includes an engaging section, a base section, and a stress section sequentially coupled to each other and bent with respect to each other. The base section is pivotally coupled to the fixing frame, and the engaging section is engaged between the inner and outer rails. When the stress section is controlled by an external force, the engaging section is driven to release the engagement between the inner rail and the outer rail, so as to ensure the accurate action of the engaging structure and allow the engaging member to have better structural strength, smoother control, and more accurate engagement and disengagement effects.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 22, 2020
    Inventors: Jeffrey Chung-Chiang HSI, Yu-Ching LEE, Jie GAO, Jin-Zhou XIE, Xing-He LIN
  • Patent number: 10811518
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10794872
    Abstract: A system and method for determining clearance between a fabrication tool and a workpiece is provided. In an exemplary embodiment, the method includes receiving a substrate within a tool such that a gap is defined there between. A transducer disposed on a bottom surface of the substrate opposite the gap provides an acoustic signal that is conducted through the substrate. The transducer also receives a first echo from a top surface of the substrate that defines the gap and a second echo from a bottom surface of the tool that further defines the gap. A width of the gap is measured based on the first echo and the second echo. In some embodiments, the bottom surface of the tool is a bottom surface of a nozzle, and the nozzle provides a liquid or a gas in the gap while the transducer is receiving the first and second echoes.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Publication number: 20200306185
    Abstract: An antibacterial colloid, comprising: a plurality of metal nanoparticles. wherein the plurality of metal nanoparticles have an average particle diameter less than 10 nm; a plurality of metal ions, wherein the plurality of metal ions have a concentration greater than 20 ppm; and a medium, wherein the medium comprises a protein component containing at least a functional group for reduction, wherein the antibacterial colloid is free from nitrate ions.
    Type: Application
    Filed: August 21, 2019
    Publication date: October 1, 2020
    Applicant: Kaohsiung Medical University
    Inventors: Chi-Jen Shih, Chung-Lin Lee, Yuan-Ting Yang-Wang, Yu-Ching Chiang, Yu-Hsuan Chen
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Publication number: 20200282870
    Abstract: An electric drive mechanism of a seat rail includes a front frame, a rear frame, a gear assembly, a lead screw and a bumper. The front frame and rear frame are separated from each other and fixed to an outer rail of a slide rail; the lead screw is spanned across the front frame and rear frame; the gear assembly driven by a driving device is fixed to an inner rail of the slide rail and engaged with the lead screw; the bumper is installed at the rear frame provide a buffering effect between the gear assembly and the rear frame, so as to prevent the production of abnormal sounds caused by colliding the gear assembly with the rear frame directly.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Jeffrey Chung-Chiang HSI, Yu-Ching LEE, Jie GAO, Jin-Zhou XIE, Xing-He LIN
  • Patent number: 10766951
    Abstract: Anti-CaENO1 antibodies and humanized antibodies are provided as an effective diagnostic agent or a therapeutic treatment against infections caused by Candida spp., preferably Candida albicans, Candida tropicalis, fluconazole resistance Candida spp., Streptococcus, Staphylococcus.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 8, 2020
    Assignee: TAIPEI MEDICAL UNIVERSITY
    Inventors: Sy-Jye Leu, Yi-Yuan Yang, Yu-Ching Lee, Ching-Hua Su, Ko-Jiunn Liu, Hsiu-Jung Lo, Yun-Liang Yang
  • Publication number: 20200279759
    Abstract: A transportation container is provided with a container body constructed of a top wall, a bottom wall, a rear wall, and two sidewalls forming a front opening for loading or unloading a reticle pod into or out of the container body; a lid for opening and closing the front opening; and a lift plate above the container body configured to connect to a carrier of an overhead hoist transfer (OHT) system.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Yu-Ching Lee, Yu-Piao Fang
  • Patent number: 10737581
    Abstract: An adaptive power supply system for an unmanned vehicle and an operation method thereof are provided. The adaptive power supply system includes an adaptive power supply, a battery, a sensing circuit, and a power dispatch controller. The output terminal of the adaptive power supply powers the load circuit of the unmanned vehicle. The battery is coupled to the output terminal of the adaptive power supply. The sensing circuit senses the output of the output terminal of the adaptive power supply and the output of the battery. The power dispatch controller controls the output of the output terminal of the adaptive power supply according to the sensing result of the sensing circuit. The power dispatch controller determines whether one or both of the adaptive power supply and the battery power the load circuit by adjusting the output of the adaptive power supply.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 11, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Hung Lin, Yu-Sheng Lee, Chih-Wei Hsu, Yung-Chao Chen, Hsien-Ching Hsieh
  • Publication number: 20200239560
    Abstract: The invention relates to anti-EGF like domain multiple 6 antibody (anti-EGFL6 antibody) and cancer detection (or diagnosis) and treatment using the anti-EGFL6 antibody. The present invention creates anti-EGFL6 antibodies, particularly, a single-chain antibody fragments (scFv) and humanized antibody, which have ability in binding to EGFL6 and in inhibiting angiogenesis and cancer cell growth.
    Type: Application
    Filed: September 28, 2018
    Publication date: July 30, 2020
    Inventors: YU-CHING LEE, SHIOW-LIN PAN, Wei-Chun HUANGFU, Tsui-Chin HUANG, Po-Li WEI, Han-Li HUANG, Chun-Chun CHENG, Cheng-Chiao HUANG, Keng-Chang TSAI, Kun-Tu YEH
  • Patent number: 10727344
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Publication number: 20200227534
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Patent number: 10714592
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10691017
    Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin