Abstract: A double-layer rack includes a PCIe card frame, a network card frame, a PCIe riser card and a network card connector assembly. The PCIe card frame is stacked on the network card frame. The network card frame has a network card accommodation space for selectively receiving one OCP network card, two OCP network cards or one data processing unit. The PCIe riser card is disposed in the PCIe accommodation space. The network card connector assembly is disposed in the network card accommodation space. The double-layer rack further includes a blocker component and a divider plate selectively and removably disposed on the network card frame, so that the network card accommodation space forms various accommodation space configurations for selectively receiving the one OCP network card, the two OCP network cards or the one data processing unit.

Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

Abstract: A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.

Abstract: An imaging lens assembly includes optical elements and a light path folding mechanism. The light path folding mechanism is disposed on the optical axis to fold an optical axis at least once, and includes a light folding element, a light blocking structure and a nanostructure layer. The light folding element includes a reflecting surface, an incident surface and an exit surface. The reflecting surface is configured to fold an incident light path towards an exit light path. The light blocking structure is disposed on at least one of the incident surface and the exit surface, and includes a main light blocking portion located on a peripheral portion closest to the optical axis on a cross section passing through the optical axis. The nanostructure layer is continuously distributed over at least one of the incident surface and the exit surface and the main light blocking portion.

Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.

Abstract: The present disclosure provides a biochemical test chip, including an insulating substrate, an electrode unit, a first insulating septum, a reactive layer and a second insulating septum. The electrode unit is located on the insulating substrate. The electrode unit includes a working electrode and a counter electrode. A current density of the counter electrode is greater than a current density of the working electrode. The first insulating septum is located on the electrode unit. The first insulating septum has an opening, which at least partially exposes the electrode unit. The reactive layer is located in the opening and is electrically connected to the electrode unit. The second insulating septum is located on the first insulating septum.

Abstract: A fluid material dispensing apparatus include: a first nozzle; a second nozzle; a pump, arranged to operably extract a fluid material from the material container and to operably push the fluid material to flow toward the first nozzle; a material-temperature adjustment device, coupled with the first nozzle; a water-temperature adjustment device, coupled between a water input port and the second nozzle; and a control circuit for controlling the material-temperature adjustment device to adjust a temperature of the fluid material to produce and output a temperature-adjusted material to the first nozzle; wherein the control circuit also controls the water-temperature adjustment device to adjust a temperature of water transmitted from the water input port to produce and output a temperature-adjusted water to the second nozzle.

Abstract: A material dispensing device includes: a target nozzle for dispensing a target material to a target container; a pump arranged to operably extract the target material from the material container and to operably push the target material to flow toward the target nozzle; a material drainage port; a flow direction switch device, coupled with the target nozzle and the material drainage port, and arranged to operably receive the target material; and a control circuit. When the material dispensing device needs to output the target material to the target container, if the control circuit determines that a temperature of the target material inside the material dispensing device reaches a predetermined temperature, the control circuit controls the flow direction switch device to guide the target material to flow toward the target nozzle, so as to dispense the target material into the target container through the target nozzle.

Abstract: An integrated circuit (IC) package includes a first integrated circuit (IC) device. An interconnection structure is disposed over the first IC device in a cross-sectional side view. The interconnection structure includes a plurality of interconnection components. A cavity is disposed in the interconnection structure in the cross-sectional side view. A second IC device is disposed at least partially within the cavity in the cross-sectional side view. The second IC device is electrically coupled to the first IC device through at least a subset of the interconnection components of the interconnection structure. A non-metallic material partially fills the cavity. The second IC device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in a top view.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A semiconductor structure includes an interconnect structure, a passivation structure, a first capacitor, and a contact feature. The interconnect structure is disposed over a semiconductor substrate. The passivation structure is disposed over the interconnect structure. The first capacitor is disposed within the passivation structure. The contact feature is disposed over the passivation structure, wherein the first capacitor is proximal to a corner of the contact feature. A method of manufacturing the semiconductor structure is also provided.

Abstract: A control device includes a first capacitor, a drive controller, a constant current source, a discharge-controlled current source, a current mirror, and a sample-and-hold circuit. The constant current source generates a constant current. The discharge-controlled current source is coupled to the constant current source and the first capacitor. The current mirror is coupled to the first capacitor and the primary side of a primary-side switch. The current mirror generates a copy current, thereby generating a copy voltage across the first capacitor. When the drive controller turns on the primary-side switch, the sample-and-hold circuit drives the discharge-controlled current source to sample and hold a control current from the constant current and the copy current. When the node voltage is higher than the copy voltage, the comparison circuit drives the drive controller to turn off the primary-side switch.

Abstract: An imaging lens assembly has an optical axis and includes a plastic lens element set. The plastic lens element set includes two plastic lens elements and at least one anti-reflective layer. The two plastic lens elements, in order from an object side to an image side along the optical axis are a first plastic lens element and a second plastic lens element. The anti-reflective layer has a nanostructure and is disposed on at least one of an image-side surface of the first plastic lens element and an object-side surface of the second plastic lens element.

Abstract: A defect inspection system is disclosed, and comprises a linear light source, N number of cameras, a display device, a tag reader, and a modular electronic device, in which the linear light source, the cameras and the modular electronic device are used for conducting a defect inspection of an article. On the other hand, the display device, the tag reader and the modular electronic device are adopted for conducting in production of at least one labeled example. Therefore, the modular electronic device is allowed to apply a machine learning process to an image classifier under using a training dataset containing the labeled examples, thereby producing at least one new defect recognition model or updating the existing defect recognition model.

Abstract: A p-GaN high-electron-mobility transistor, includes a substrate, a channel layer stacked on the substrate, a supply layer stacked on the channel layer, a first doped layer stacked on the supply layer, a second doped layer stacked on the first doped layer, and a third doped layer stacked on the second doped layer. A doping concentration of the first doped layer and the doping concentration of the third doped layer are lower than a doping concentration of the second doped layer. A gate is located on the third doped layer, and a source and a drain are electrically connected to the channel layer and the supply layer, respectively.

Abstract: An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.

Abstract: The disclosure provides an electronic fuse (eFuse) device and an operation method thereof. The eFuse device includes an eFuse, a readout circuit, a register, and a safety control device. The readout circuit reads out target data recorded by the eFuse to the register and the safety control device. The safety control device compares the target data provided by the readout circuit with the target data provided by the register to determine whether a soft error occurs in the target data stored in the register. When the soft error occurs in the target data stored in the register, the readout circuit reads out the target data recorded by the eFuse again to the register and the safety control device.

Abstract: An antenna system for improved satellite communication with a ground-based terminal device includes a first antenna, a feeding point, and a phase modulation unit. The first antenna is on a surface of a back cover of the terminal device, and the first antenna comprises a plurality of radiation units in an array. The feeding point feeds power and signals to the first antenna. The phase modulation unit can adjust the transmission phase of the different radiation units within the first antenna. The present disclosure also provides a wireless terminal.