Patents by Inventor Yu-Chu Lin

Yu-Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018258
    Abstract: A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20210126048
    Abstract: A micro LED display panel includes a display area, a plurality of micro light-emitting elements and a plurality of micro control elements. The plurality of micro light-emitting elements is disposed in the display area and include a plurality of first color micro LEDs and a plurality of second color micro LEDs. A light wavelength of each of the first color micro LEDs is different from a light wavelength of each of the second color micro LEDs. The plurality of micro control elements is disposed in the display area, and include a plurality of first color micro circuit-chips and a plurality of second color micro circuit-chips. The plurality of first color micro circuit-chips control the plurality of first color micro LEDs, and the plurality of second color micro circuit-chips control the plurality of second color micro LEDs.
    Type: Application
    Filed: January 7, 2021
    Publication date: April 29, 2021
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 10992064
    Abstract: A mobile device includes a WLAN (Wireless Local Area Network) module, a WWAN (Wireless Wide Area Network) module, a first antenna element, a second antenna element, a third antenna element, a fourth antenna element, a first switch element, and a second switch element. The WLAN module has a first port, a second port, and a first control port. The WWAN module has a third port, a fourth port, a fifth port, and a sixth port. The first antenna element is coupled to the third port. The first switch element couples the second antenna element to the first port or the fourth port according to a first control signal. The second switch element couples the third antenna element to the second port or the fifth port according to a second control signal. The fourth antenna element is coupled to the sixth port.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 27, 2021
    Assignee: WISTRON CORP.
    Inventors: Yu-Chia Chang, Wan Chu Wei, Chun-Hong Kuo, Tsung-Te Lin
  • Publication number: 20210043774
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Szu-Hsien LU, Yu-Chu LIN
  • Publication number: 20210036118
    Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.
    Type: Application
    Filed: May 20, 2020
    Publication date: February 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG
  • Patent number: 10877573
    Abstract: A handheld apparatus, a control method thereof of a presenting mode and a computer-readable recording medium are provided. The handheld apparatus includes at least one first sensor, a second sensor, a screen and a processor. The first sensor is disposed on the handheld apparatus. The second sensor detects orientation. The handheld apparatus has an auto-rotate screen function of automatically adjusting a presenting mode of the screen to a portrait mode or a landscape mode according to the orientation. The processor determines whether the handheld apparatus is in a hold state according to sensing data of the first sensor. In response to determining that the handheld apparatus is in the hold state, the processor locks the presenting mode according to the presenting mode currently performed by the handheld apparatus without adjusting the presenting mode according to the auto-rotate screen function. Accordingly, a convenient operation of the presenting mode is provided.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: December 29, 2020
    Assignee: HTC Corporation
    Inventors: Shuo-Fang Jeng, Yu-Cheng Hung, Shih-Lung Lin, Kuan-Wei Li, Pei-Chun Tsai, Yu-Chu Lin, Ching-Yung Wu
  • Patent number: 10818804
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Szu-Hsien Lu, Yu-Chu Lin
  • Patent number: 10710203
    Abstract: A universal jig is provided for clamping wind turbine blades. The jig has a rectangle-like shape forming a space for clamping a blade at the blade root or the blade body. The jig comprises a set of vertically-moving parts; a set of horizontally-moving parts; a plurality of adjusted pads; and a plurality of positioning parts. The vertically-moving parts comprise two upper connecting posts and two lower connecting posts sheathed with each other separately to form two length sides of the jig. The horizontally-moving parts comprise two left connecting posts and two right connecting posts. The adjusted pads are locked on the left and the right connecting posts. The positioning parts are locked at the upper and the lower connecting posts of the length sides of the jig and are locked at the left and the right connecting posts of the width sides of the jig.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 14, 2020
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL
    Inventors: Yu-Chu Lin, Yan-Ting Lin, Wei-Nian Su, Chin-Cheng Huang
  • Publication number: 20190332191
    Abstract: A handheld apparatus, a control method thereof of a presenting mode and a computer-readable recording medium are provided. The handheld apparatus includes at least one first sensor, a second sensor, a screen and a processor. The first sensor is disposed on the handheld apparatus. The second sensor detects orientation. The handheld apparatus has an auto-rotate screen function of automatically adjusting a presenting mode of the screen to a portrait mode or a landscape mode according to the orientation. The processor determines whether the handheld apparatus is in a hold state according to sensing data of the first sensor. In response to determining that the handheld apparatus is in the hold state, the processor locks the presenting mode according to the presenting mode currently performed by the handheld apparatus without adjusting the presenting mode according to the auto-rotate screen function. Accordingly, a convenient operation of the presenting mode is provided.
    Type: Application
    Filed: September 3, 2018
    Publication date: October 31, 2019
    Applicant: HTC Corporation
    Inventors: Shuo-Fang Jeng, Yu-Cheng Hung, Shih-Lung Lin, Kuan-Wei Li, Pei-Chun Tsai, Yu-Chu Lin, Ching-Yung Wu
  • Publication number: 20190314942
    Abstract: A universal jig is provided for clamping wind turbine blades. The jig has a rectangle-like shape forming a space for clamping a blade at the blade root or the blade body. The jig comprises a set of vertically-moving parts; a set of horizontally-moving parts; a plurality of adjusted pads; and a plurality of positioning parts. The vertically-moving parts comprise two upper connecting posts and two lower connecting posts sheathed with each other separately to form two length sides of the jig. The horizontally-moving parts comprise two left connecting posts and two right connecting posts. The adjusted pads are locked on the left and the right connecting posts. The positioning parts are locked at the upper and the lower connecting posts of the length sides of the jig and are locked at the left and the right connecting posts of the width sides of the jig.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Inventors: Yu-Chu Lin, Yan-Ting Lin, Wei-Nian Su, Chin-Cheng Huang
  • Patent number: 10283604
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Hsien Lu, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu, Yu-Chu Lin, Jyun-Guan Jhou
  • Publication number: 20190093628
    Abstract: A vertical axis wind turbine having a varying length of a rotational diameter includes a plurality of vertical blades connected to a central shaft of a generator, the plurality of blades being provided at equal intervals on the outer circumference side of the central shaft, and each of the blades is provided with at least one support shaft member extending towards the central shaft, and in between each of the support shaft member and the central shaft is provided, respectively, with an elastic telescopic assembly, and each of the elastic telescopic assemblies is respectively driven by the centrifugal force of the blades above a rated speed to drive the support shaft member to extend outwardly, so that the rotation radius of each blade from the central shaft increases as the rotational speed increases.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Inventors: YAN-TING LIN, YU-CHU LIN, CHIN-CHENG HUANG
  • Patent number: 10141401
    Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
  • Patent number: 9825046
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu
  • Publication number: 20170263464
    Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Yu-Chu LIN, Jyun-Guan JHOU
  • Publication number: 20170194336
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: Yu-Chu LIN, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU
  • Patent number: 9666668
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
  • Publication number: 20170125602
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Szu-Hsien LU, Yu-Chu LIN
  • Publication number: 20170117355
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Yu-Chu LIN, Jyun-Guan JHOU
  • Publication number: 20170033047
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Szu-Hsien LU, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU, Yu-Chu LIN, Jyun-Guan JHOU