Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A method for manufacturing a memory device is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.

Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.

Abstract: A handheld apparatus, a control method thereof of a presenting mode and a computer-readable recording medium are provided. The handheld apparatus includes at least one first sensor, a second sensor, a screen and a processor. The first sensor is disposed on the handheld apparatus. The second sensor detects orientation. The handheld apparatus has an auto-rotate screen function of automatically adjusting a presenting mode of the screen to a portrait mode or a landscape mode according to the orientation. The processor determines whether the handheld apparatus is in a hold state according to sensing data of the first sensor. In response to determining that the handheld apparatus is in the hold state, the processor locks the presenting mode according to the presenting mode currently performed by the handheld apparatus without adjusting the presenting mode according to the auto-rotate screen function. Accordingly, a convenient operation of the presenting mode is provided.

Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.

Abstract: A universal jig is provided for clamping wind turbine blades. The jig has a rectangle-like shape forming a space for clamping a blade at the blade root or the blade body. The jig comprises a set of vertically-moving parts; a set of horizontally-moving parts; a plurality of adjusted pads; and a plurality of positioning parts. The vertically-moving parts comprise two upper connecting posts and two lower connecting posts sheathed with each other separately to form two length sides of the jig. The horizontally-moving parts comprise two left connecting posts and two right connecting posts. The adjusted pads are locked on the left and the right connecting posts. The positioning parts are locked at the upper and the lower connecting posts of the length sides of the jig and are locked at the left and the right connecting posts of the width sides of the jig.

Abstract: A handheld apparatus, a control method thereof of a presenting mode and a computer-readable recording medium are provided. The handheld apparatus includes at least one first sensor, a second sensor, a screen and a processor. The first sensor is disposed on the handheld apparatus. The second sensor detects orientation. The handheld apparatus has an auto-rotate screen function of automatically adjusting a presenting mode of the screen to a portrait mode or a landscape mode according to the orientation. The processor determines whether the handheld apparatus is in a hold state according to sensing data of the first sensor. In response to determining that the handheld apparatus is in the hold state, the processor locks the presenting mode according to the presenting mode currently performed by the handheld apparatus without adjusting the presenting mode according to the auto-rotate screen function. Accordingly, a convenient operation of the presenting mode is provided.

Abstract: A universal jig is provided for clamping wind turbine blades. The jig has a rectangle-like shape forming a space for clamping a blade at the blade root or the blade body. The jig comprises a set of vertically-moving parts; a set of horizontally-moving parts; a plurality of adjusted pads; and a plurality of positioning parts. The vertically-moving parts comprise two upper connecting posts and two lower connecting posts sheathed with each other separately to form two length sides of the jig. The horizontally-moving parts comprise two left connecting posts and two right connecting posts. The adjusted pads are locked on the left and the right connecting posts. The positioning parts are locked at the upper and the lower connecting posts of the length sides of the jig and are locked at the left and the right connecting posts of the width sides of the jig.

Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.

Abstract: A vertical axis wind turbine having a varying length of a rotational diameter includes a plurality of vertical blades connected to a central shaft of a generator, the plurality of blades being provided at equal intervals on the outer circumference side of the central shaft, and each of the blades is provided with at least one support shaft member extending towards the central shaft, and in between each of the support shaft member and the central shaft is provided, respectively, with an elastic telescopic assembly, and each of the elastic telescopic assemblies is respectively driven by the centrifugal force of the blades above a rated speed to drive the support shaft member to extend outwardly, so that the rotation radius of each blade from the central shaft increases as the rotational speed increases.

Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.