Patents by Inventor Yu-Chun Huang

Yu-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240396103
    Abstract: An energy storage device capable of suppressing battery spread of battery fire includes a control module and a plurality of battery modules, and the battery modules respectively include an accommodation space, a plurality of battery packs, a plurality of temperature sensors and a controller. The controller provides a first control signal to notify the control module based on an ambient temperature detected by one of the temperature sensors being greater than or equal to a first specific temperature range. The control module is used to transfer a battery capacity of an abnormal battery module of the battery modules providing the first control signal to a backup energy storage module, and the backup energy storage module includes the battery modules except the abnormal battery module or a next-stage device.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Inventors: Chung-Hsing CHANG, Wen-Yi CHEN, Way-Lung WU, Teng-Chi HUANG, Shi-Cheng TONG, Yong-Han CHEN, Yu-Chun WANG
  • Publication number: 20240387279
    Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Yen-Chun Huang, Shu Ling Liao, Fang-Yi Liao, Yu-Chang Lin
  • Patent number: 12149049
    Abstract: A vertical-cavity surface-emitting laser includes a substrate. A first mirror is disposed on the substrate. An active layer is disposed on the first mirror. An oxide layer is disposed on the active layer. An aperture is disposed on the active layer. The aperture is surrounded by the oxide layer. A second mirror is disposed on the aperture and the oxide layer. A high-contrast grating is disposed on the second mirror. The high-contrast grating includes a first grating element and a second grating element, and the first grating element and the second grating element are spaced apart from each other with an air gap therebetween. A passivation layer is disposed on the high-contrast grating. A first thickness of the passivation layer on a top surface of the first grating element is greater than a second thickness of the passivation layer on a first sidewall of the first grating element.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: November 19, 2024
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Yu-Chun Chen, Yu-Hsuan Huang, Chia-Ta Chang
  • Patent number: 12148831
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Meng-Chun Chang
  • Patent number: 12148672
    Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Shu Ling Liao, Fang-Yi Liao, Yu-Chang Lin
  • Publication number: 20240374944
    Abstract: A battery module capable of suppressing spread of battery fire including a case, a plurality of battery packs, a plurality of temperature sensors, an energy consumption module and a controller. The case forms an accommodation space, and the battery packs is accommodated in the accommodation space. The temperature sensors are dispersedly configured to the accommodation space, and the temperature sensors respectively detect an ambient temperature around configure locations. The controller is coupled to the temperature sensors, and when the ambient temperature detected by one of the temperature sensors is greater than or equal to a first specific temperature range, the controller controls the energy consumption module to consume a battery capacity of at least one battery pack around the one of the temperature sensors.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventors: Chung-Hsing CHANG, Wen-Yi CHEN, Way-Lung WU, Teng-Chi HUANG, Shi-Cheng TONG, Yong-Han CHEN, Yu-Chun WANG
  • Publication number: 20240363702
    Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng, Wei Ju Lee
  • Patent number: 12117573
    Abstract: A high-power seismic wave early warning method is provided to use an earliest-arriving seismic wave to estimate a maximum power value of a later-arriving high-power seismic wave for a target site. When the estimated maximum power value of the later-arriving high-power seismic wave is greater than a warning value, an earthquake early warning is transmitted to an earthquake early warning device that is located at the target site.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: October 15, 2024
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chung-Che Chou, Shu-Hsien Chao, Che-Min Lin, Kung-Chun Lu, Yu-Tzu Huang
  • Patent number: 12105562
    Abstract: A portable electronic device including a main display having a locking recess at a side edge and at least one external display detachable relative to the side edge of the main display is provided. The external display includes a body, and at least one latch pivoted to the body. The latch is pivoted to the body to be swiveled out of or into the body. An opening of the locking recess faces obliquely upward and faces away from a direction of gravity when the main display is standing, the at least one latch swiveled out of the body faces obliquely downward and faces forward the direction of gravity to be inserted into the locking recess, and the at least one external display is hung on at the side edge of the main display by a weight of the at least one external display.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: October 1, 2024
    Assignee: Acer Incorporated
    Inventors: Yu-Shih Wang, Yi-Ta Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Publication number: 20240321780
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240321572
    Abstract: Provided are semiconductor devices and methods for manufacturing semiconductor devices. A method deposits conformal material to form a conformal liner in the trench and modifies the conformal liner such an upper liner portion is modified more than a lower liner portion. The deposition and modifying steps are repeated while a rate of deposition of the conformal material over a non-modified surface of the conformal liner is faster than a rate of deposition of the conformal material over a modified surface of the conformal liner to form a remaining unfilled gap with a V-shape. The method further includes depositing a conformal material in the remaining unfilled gap.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Fong Lin, Yen-Chun Huang, Zhen-Cheng Wu, Chi On Chui, Chih-Tang Peng, Yu Ying Chen
  • Publication number: 20240313990
    Abstract: An example non-transitory machine-readable storage medium comprising instructions executable by a processing resource of a computing device to cause the computing device to: receive a video feed of a participant in a video conference; identify the participants within the video feed; determine a probability that a characteristic is being experienced by the participant; determine a relevancy score of the participant based on the probability that the characteristic is being experienced by the participant; and display the participant relative to other participants in the video conference based on the relevancy score.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Pei Hsuan Li, Rose Hedderman, Sarah Shiraz, Yu Chun Huang
  • Patent number: 12094938
    Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng, Wei Ju Lee
  • Patent number: 12096657
    Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: September 17, 2024
    Assignee: Apple Inc.
    Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
  • Publication number: 20240304657
    Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.
    Type: Application
    Filed: March 29, 2023
    Publication date: September 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Chun Teng, Ming-Che Tsai, Ping-Chia Shih, Yi-Chang Huang, Wen-Lin Wang, Yu-Fan Hu, Ssu-Yin Liu, Yu-Nong Chen, Pei-Tsen Shiu, Cheng-Tzung Tsai
  • Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12077873
    Abstract: A method for manufacturing nitride catalyst is provided, which includes putting a Ru target and an M target into a nitrogen-containing atmosphere, in which M is Ni, Co, Fe, Mn, Cr, V, Ti, Cu, or Zn. The method also includes providing powers to the Ru target and the M target, respectively. The method also includes providing ions to bombard the Ru target and the M target for depositing MxRuyN2 on a substrate by sputtering, wherein 0<x<1.3, 0.7<y<2, and x+y=2, wherein MxRuyZ2 is cubic crystal system or amorphous.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: September 3, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuo-Hsin Lin, Li-Duan Tsai, Wen-Hsuan Chao, Chiu-Ping Huang, Pin-Hsin Yang, Hsiao-Chun Huang, Jiunn-Nan Lin, Yu-Ming Lin
  • Patent number: 12066871
    Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a rotating shaft fixed to the second body. When the second body rotates relative to the first body, the rotating shaft slides along an arc-shaped path to increase or decrease a distance between a lower edge of the second body and a back side of the first body.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: August 20, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Ta Huang, Yu-Shih Wang, Cheng-Nan Ling, Chih-Chun Liu
  • Publication number: 20240258123
    Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.
    Type: Application
    Filed: April 1, 2024
    Publication date: August 1, 2024
    Inventors: Sheng-chun YANG, Chih-Lung CHENG, Yi-Ming LIN, Po-Chih HUANG, Yu-Hsiang JUAN, Xuan-Yang ZHENG
  • Publication number: 20240255435
    Abstract: A defect inspection method is disclosed. The method includes acquiring a plurality of first images of a first specimen in a first resolution. The method includes acquiring a plurality of second images of the first specimen in a second resolution, the second resolution being different from the first resolution. The method includes training a machine learning model with a training set, wherein the training set comprises at least the plurality of first images of the first specimen and the plurality of second images of the first specimen. The method includes acquiring a third image of a second specimen in the first resolution. The method includes inputting the third image into the trained machine learning model. The method includes generating, based on the trained machine learning model, a fourth image of the second specimen in the second resolution.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Chien Chiu, Ting-Chun Peng, To-Yu Chen, Mao-Chih Huang