Patents by Inventor Yu-Chun Lin

Yu-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262409
    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Inventors: Ku-Feng LIN, Yu-Der CHIH, Yi-Chun SHIH, Chia-Fu LEE
  • Patent number: 11417800
    Abstract: A micro semiconductor device and a micro semiconductor display are provided. The micro semiconductor device includes an epitaxial structure, a first electrode, a second electrode and a supporting layer. The epitaxial structure has a bottom surface and a top surface, wherein the bottom surface is defined as a central region and a peripheral region. A first electrode and a second electrode are disposed on the central region of the bottom surface of the epitaxial structure, or the first electrode is disposed on the central region of the bottom surface of the epitaxial structure and the second electrode is disposed on the top surface of the epitaxial structure. The supporting layer is disposed on the peripheral region of the bottom surface of the epitaxial structure.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: August 16, 2022
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20220251831
    Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 11, 2022
    Applicant: MINIWIZ CO.,LTD.
    Inventors: Chian-Chi HUANG, Tzu-Wei LIU, Jui-Ping CHEN, Yu-Ying YAI, Yu-Tung HSING, Pei-Yi HUANG, Min-Wei LIN, Yi-Chun CHANG, Ling-Hsiang WENG
  • Publication number: 20220248566
    Abstract: A computer includes a casing, an electronic assembly, and a water cooling assembly. The casing, forms an accommodation space. The casing has an interior fluid channel located at at least one side of the casing, and a fluid inlet and a fluid outlet which are in fluid communication with the interior fluid channel. The electronic assembly is located in the accommodation space. The water cooling assembly includes a first water block and a radiator. The first water block is in thermal contact with the electronic assembly, the first water block, the radiator, and the interior fluid channel located at the at least one side of the casing are in fluid communication with each other so as to form a circulation channel, and the fluid inlet and the fluid outlet of the casing are respectively in fluid communication with the radiator and the first water block.
    Type: Application
    Filed: December 21, 2021
    Publication date: August 4, 2022
    Applicant: COOLER MASTER CO., LTD.
    Inventors: Ying-Chun CHEN, Yu-Te WEI, Tsung-Wei LIN
  • Publication number: 20220236766
    Abstract: An electronic device assembly is provided, including an electronic device body and a detachable lens module. The electronic device body has a housing and a first joining unit, wherein the first joining unit is disposed on the housing. The detachable lens module is detachably assembled onto the housing and has a second joining unit, wherein the first joining unit is joined to the second joining unit to electrically connect the detachable lens module to the electronic device body.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Yi-Ta Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai, Chi-Hung Lai, Wu-Chen Lee, Pin-Chueh Lin, Chih-Wei Liao, Ting-Wen Pai, Wen-Chieh Chen
  • Patent number: 11387105
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Patent number: 11387387
    Abstract: A micro light emitting device display apparatus including a circuit substrate, a plurality of micro light emitting devices, a first common electrode layer, and a second common electrode layer is provided. The micro light emitting devices are disposed on the circuit substrate and individually include an epitaxial structure and a first-type electrode and a second-type electrode respectively disposed on two side surfaces of the epitaxial structure opposite to each other. The first common electrode layer is disposed on the circuit substrate and directly covers the plurality of first-type electrodes of the micro light emitting devices. The second common electrode layer is disposed between the micro light emitting devices. The first common electrode layer is electrically connected to the second common electrode layer.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 12, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling Wu, Yen-Yeh Chen, Yi-Min Su, Yi-Chun Shih, Bo-Wei Wu, Yu-Yun Lo, Ying-Ting Lin, Tzu-Yang Lin
  • Publication number: 20220216343
    Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Inventors: Yu-Chun SHEN, Chi-Chung JEN, Ya-Chi HUNG, Yu-Chu LIN, Wen-Chih CHIANG
  • Publication number: 20220216165
    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong LIN, Kuo-Yen LIU, Hsin-Chun CHANG, Tzu-Li LEE, Yu-Ching LEE, Yih-Ching WANG
  • Patent number: 11379487
    Abstract: Enhancing a data query is provided. A knowledge base is searched for information corresponding to the data query. It is determined whether a query result is greater than a query result threshold level of information for the data query based on an identified query intent and keywords of the data query. In response to determining that the query result is not greater than the query result threshold level of information for the data query, a set of questions is sent to a personal digital agent of a client device that sent the data query for additional information based on the identified query intent and keywords. Analytic concepts answering the set of questions are received from analytic modules of the personal digital agent that are based on IoT-based personal data corresponding to a user of the client device. The data query is enhanced using the analytic concepts.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ching-Wei Cheng, Yu-chun Lin, Hsin-Yu Hsieh, Chih-Hsiung Liu, Tsai-Hsuan Hsieh
  • Publication number: 20220209595
    Abstract: A synchronous reluctance motor includes a rotor and a stator surrounding the rotor. The rotator includes a rotatable shaft and magnetic flux barrier layers arranged radially. One of the magnetic flux barrier layers closest to the stator is filled with a conductor, and one of the magnetic flux barrier layers closest to the rotating shaft is a void.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 30, 2022
    Inventors: Pei-Chun SHIH, Yu-Wei HSU, Sheng-Chan YEN, Ta-Yin LUO, Hsin-Nan LIN, Guo-Jhih YAN, Cheng-Tsung LIU
  • Patent number: 11373690
    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ku-Feng Lin, Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee
  • Patent number: 11374136
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11372297
    Abstract: A display panel including a pixel array substrate, an opposite substrate, and a display media is provided. The pixel array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel units, and a gate driving circuit. The gate driving circuit including a plurality of first signal lines, a plurality of second signal lines, a plurality of dummy signal lines, and a plurality of contact structures is disposed in a peripheral region of the substrate. Each of the second signal lines is electrically connected to one corresponding first signal line. Each of the dummy signal lines is electrically connected to one corresponding second signal line via one corresponding contact structure. Each of the first signal lines is electrically connected to the corresponding second signal line via one corresponding contact structure.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: June 28, 2022
    Assignee: Au Optronics Corporation
    Inventors: Cheng-Hung Ko, Yi-Fu Chen, Yu-Sen Chang, Chia-Heng Chen, Hsiao-Chun Chen, You-Ying Lin, Cheng-An Hsieh
  • Patent number: 11374382
    Abstract: A method for increasing the bandwidth of an electroabsorption modulator (EAM) includes the following steps. First, a plurality of p-i-n active waveguides for the EAM are defined on a p-i-n optical waveguide forming an EAM having a shorter p-i-n active waveguide length. Then, the bandwidth of the EAM can be increased. Second, the high-impedance transmission lines are used in series to connect the EAM sections to reduce the microwave reflection and then increase the device bandwidth. Finally, the impedance-controlled transmission lines for the signal input and output can not only reduce the parasitic effects resulting from packaging, but also reduce the microwave reflection resulting from the impedance mismatch at the device input and load.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 28, 2022
    Assignee: LUXNET CORPORATION
    Inventors: Fang-Jeng Lin, Yu-Chun Fan, Pi-Cheng Law, Yi-Ching Chiu
  • Patent number: 11341881
    Abstract: A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the input terminal. The first control bias unit includes a third transistor and a fourth transistor coupled to the first transistor and second transistor respectively and their gates are controlled by a first bias. The output stage includes a fifth transistor and a sixth transistor coupled to the third transistor and fourth transistor respectively and their gates are coupled to the first output terminal and second output terminal. The second control bias unit includes a seventh transistor and an eighth transistor coupled to the fifth transistor and sixth transistor respectively and their gates are controlled by a second bias.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 24, 2022
    Assignee: Raydium Semiconductor Corporation
    Inventors: Po-Cheng Lin, Yu-Chun Lin
  • Patent number: 11327604
    Abstract: A touch sensing circuit for use in a touch sensitive device includes: an integrator, a first switching unit and a control signal generator. The integrator, coupled to at least one sensing electrode of a touch panel in the touch sensitive device, and arranged to collect charges on the at least one sensing electrode and accordingly generate an output sensed signal. The first switching unit is arranged to selectively couple a first end of the at least one sensing electrode to a reference voltage level according to a first mask signal. The control signal generator is arranged to generate the first mask signal according to a synchronization signal of a display panel in the touch sensitive device, wherein the first switching unit couples the first end of the at least one sensing electrode to the reference voltage level when the synchronization signal is asserted.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: May 10, 2022
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Jia-Ming He, Yaw-Guang Chang, Yu-Chun Lin, Yi-Yang Tsai
  • Publication number: 20220108668
    Abstract: A display system includes a host and a display. The host executes a first application and a program. The program sets a first display parameter corresponding to the first application. The display receives a signal provided by the host. The signal includes a desktop. The first application is operated at a first window on the desktop. The program outputs the first display parameter to the display. The display sets the first window with the first display parameter and displays, and displays the non-first window area of the desktop with a preset display parameter.
    Type: Application
    Filed: July 7, 2021
    Publication date: April 7, 2022
    Applicant: Qisda Corporation
    Inventors: Yu-Fu FAN, Yi-Ming HUANG, Yu-Chun LIN
  • Publication number: 20220075499
    Abstract: A touch sensing circuit for use in a touch sensitive device includes: an integrator, a first switching unit and a control signal generator. The integrator, coupled to at least one sensing electrode of a touch panel in the touch sensitive device, and arranged to collect charges on the at least one sensing electrode and accordingly generate an output sensed signal. The first switching unit is arranged to selectively couple a first end of the at least one sensing electrode to a reference voltage level according to a first mask signal. The control signal generator is arranged to generate the first mask signal according to a synchronization signal of a display panel in the touch sensitive device, wherein the first switching unit couples the first end of the at least one sensing electrode to the reference voltage level when the synchronization signal is asserted.
    Type: Application
    Filed: September 7, 2020
    Publication date: March 10, 2022
    Inventors: Jia-Ming He, Yaw-Guang Chang, Yu-Chun Lin, Yi-Yang Tsai
  • Patent number: 11054895
    Abstract: A method of display user movement in a computing device of a virtual reality system is disclosed. The method comprises generating a first image in a first-person perspective with a first-person control, simulating an avatar according to a first control signal received from a controller of the virtual reality system, and generating a second image including the avatar in the first-person perspective with a third-person control, wherein the first-person perspective indicates that a user sees images as if seen through the avatar's eyes, and a field of view of the avatar is controlled by the user, the first-person control indicates that a user's movement is displayed by a relative position between the avatar and a scene of the images, and the third-person control indicates that the user's movement is displayed by different locations of the avatar in the images.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: July 6, 2021
    Assignee: HTC Corporation
    Inventors: Wei-Yi Ho, Yu-Chun Lin, Chuan-Hung Chung, Yang-Chen Fan