Patents by Inventor Yu-Chung Chin
Yu-Chung Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210104872Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL). A tunnel junction with a high doping concentration is provided in the VCSEL. An n-type semiconductor layer of the tunnel junction has stress relative to the substrate, and is doped with at least one element such that the tunnel junction not only has a high doping concentration, but also the epitaxial layer can be oxidized and the oxidation rate is relatively stable during the oxidation process. Alternatively, the n-type semiconductor layer is doped with at least two elements. As a result, the oxidation process of the VCSEL can be stably performed, and the resistance of the tunnel junction with a high doping concentration is low. The tunnel junction is suitable to be arranged between two active layers of the VCSEL or between the p-type semiconductor and the n-type semiconductor layer of the VCSEL.Type: ApplicationFiled: October 1, 2020Publication date: April 8, 2021Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Publication number: 20210091537Abstract: Provided is a high-power vertical cavity surface emitting laser diode (VCSEL), including a first epitaxial region, an active region and a second epitaxial region. One of the first epitaxial region and the second epitaxial region is an N-type epitaxial region, and the other of the first epitaxial region and the second epitaxial region includes a PN junction. The PN junction includes a P-type epitaxial layer, a tunnel junction and an N-type epitaxial layer. The tunnel junction is located between the P-type epitaxial layer and the N-type epitaxial layer, and the P-type epitaxial layer of the PN junction is closest to the active region.Type: ApplicationFiled: September 23, 2020Publication date: March 25, 2021Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Publication number: 20210075185Abstract: A measurement method for a vertical cavity surface emitting laser diode (VCSEL) and an epitaxial wafer test fixture are provided, especially the Fabry-Perot Etalon of the bottom-emitting VCSEL can be measured. When the Fabry-Perot Etalon of the bottom-emitting VCSEL is measured by a measurement apparatus, a light of the test light source of the measurement apparatus is incident from the substrate surface of the VCSEL epitaxial wafer such that the Fabry-Perot Etalon of the bottom-emitting VCSEL is acquired. Through the VCSEL epitaxial wafer test fixture, the bottom-emitting VCSEL can be directly measured by the existing measurement apparatus such that there is no need to change the optical design of the measurement apparatus, and it can prevent the VCSEL epitaxial wafer from being scratched or contaminated.Type: ApplicationFiled: September 8, 2020Publication date: March 11, 2021Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Publication number: 20210021104Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with low compressive strain DBR layer, including a GaAs substrate, a lower DBR layer, a lower spacer layer, an active region, an upper spacer layer and an upper DBR layer. The lower or the upper DBR layer includes multiple low refractive index layers and multiple high refractive index layers. The lower DBR layer, the lower spacer layer, the upper spacer layer or the upper DBR layer contains AlxGa1-xAs1-yPy, where the lattice constant of AlxGa1-xAs1-yPy is greater than that of the GaAs substrate. This can moderately reduce excessive compressive strain due to lattice mismatch or avoid tensile strain during the epitaxial growth, thereby reducing the chance of deformation and bowing of the VCSEL epitaxial wafer or cracking during manufacturing. Additionally, the VCSEL epitaxial layer can be prevented from generating excessive compressive strain or tensile strain during the epitaxial growth.Type: ApplicationFiled: July 17, 2020Publication date: January 21, 2021Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Publication number: 20200403379Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with multiple current confinement layers. A tunnel junction is generally required between two active layers to enable current to flow from one to another active layer. However, the tunnel junction will cause the current to spread in one active layer to become serious. As a result, the current in another active layer is difficult to be confined to the required area. Therefore, a current confinement layer with carrier and optical confinement functions is provided between two active layers such that the carrier and optical confinement of the active layers above and below the current confinement layer can be improved, thereby improving the performance of VCSEL. Compared with the existing VCSEL, the VCSEL with multiple current confinement layers can significantly improve the optical output power, slope efficiency and power conversion efficiency (PCE) of the VCSEL.Type: ApplicationFiled: June 19, 2020Publication date: December 24, 2020Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Publication number: 20200395737Abstract: Provided is a semiconductor laser diode. Although the materials used in the conventional technology can reduce the strain, the selections of materials are relatively limited and the carrier confinement ability is not good. To solve the above-mentioned problems, a phosphorus-containing semiconductor layer is provided in a laser diode. As such, it can effectively reduce the strain of the active region or the total strain of the laser diode, and improve the carrier confinement capability of the active region. Therefore, it can effectively reduce the total strain or significantly improve carrier confinement under appropriate conditions of the laser diode. In some cases, it has the aforesaid effects. The phosphorus-containing semiconductor layer is suitable for an active region with one or more active layers. Especially after the phosphorus-containing semiconductor layer is provided in the active region with multiple active layers, high temperature performance are significantly improved or enhanced.Type: ApplicationFiled: June 11, 2020Publication date: December 17, 2020Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai, Jhao-Hang He, Hung-Chi Hsiao
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Patent number: 10818781Abstract: Provided is a heterojunction bipolar transistor (HBT) structure with a bandgap graded hole barrier layer, including: a sub-collector layer including an N-type group III-V semiconductor on a substrate, a collector layer on the sub-collector layer and including a group III-V semiconductor, a hole barrier layer on the collector layer, a base layer on the hole barrier layer and including a P-type group III-V semiconductor, an emitter layer on the base layer and including an N-type group III-V semiconductor, an emitter cap layer on the emitter layer and including an N-type group III-V semiconductor, and an ohmic contact layer on the emitter cap layer and including an N-type group III-V semiconductor. Bandgaps of the hole barrier layer at least include a gradually increasing bandgap from the base layer towards the collector layer and a largest bandgap of the hole barrier layer is greater than bandgap of the base layer.Type: GrantFiled: February 20, 2020Date of Patent: October 27, 2020Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Kai-Yu Chen
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Publication number: 20200203510Abstract: Provided is a high ruggedness HBT, including a first emitter cap layer and a second emitter cap layer formed between an emitter layer and an ohmic contact layer, or only an emitter cap layer is formed between them. When the first and second emitter cap layers are provided, bandgaps of the first or second emitter cap layer are changed, and the ruggedness of the HBT is improved. When an emitter cap layer is provided, an electron affinity of at least a portion of the emitter cap layer is less than or approximately equal to an electron affinity of the emitter layer, and the ruggedness of the HBT is improved.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Kai-Yu Chen
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Publication number: 20200194573Abstract: Provided is a heterojunction bipolar transistor (HBT) structure with a bandgap graded hole barrier layer, including: a sub-collector layer including an N-type group III-V semiconductor on a substrate, a collector layer on the sub-collector layer and including a group III-V semiconductor, a hole barrier layer on the collector layer, a base layer on the hole barrier layer and including a P-type group III-V semiconductor, an emitter layer on the base layer and including an N-type group III-V semiconductor, an emitter cap layer on the emitter layer and including an N-type group III-V semiconductor, and an ohmic contact layer on the emitter cap layer and including an N-type group III-V semiconductor. Bandgaps of the hole barrier layer at least include a gradually increasing bandgap from the base layer towards the collector layer and a largest bandgap of the hole barrier layer is greater than bandgap of the base layer.Type: ApplicationFiled: February 20, 2020Publication date: June 18, 2020Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Kai-Yu Chen
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Publication number: 20200161421Abstract: The disclosure provides a high ruggedness HBT structure, including: a sub-collector layer on a substrate and formed of an N-type III-V semiconductor material; a collector layer on the sub-collector layer and formed of a III-V semiconductor material; a base layer on the collector layer and formed of a P-type III-V semiconductor material; an emitter layer on the base layer and formed of one of N-type semiconductor materials of InGaP, InGaAsP and InAlGaP; a first emitter cap layer on the emitter layer and formed of one of undoped or N-type semiconductor materials of AlxGa1-xAs, AlxGa1-xAs1-yNy, AlxGa1-xAs1-zPz, AlxGa1-xAs1-wSbw, and InrAlxGa1-x-rAs, x having a highest value between 0.05?x?0.4, and y, z, r, w?0.1; a second emitter cap layer on the first emitter cap layer and formed of an N-type III-V semiconductor material; and an ohmic contact layer on the second emitter cap layer and formed of an N-type III-V semiconductor material.Type: ApplicationFiled: March 5, 2019Publication date: May 21, 2020Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng, Kai-Yu Chen
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Patent number: 10651298Abstract: The disclosure provides an HBT structure with bandgap graded hole barrier layer, comprising: a sub-collector layer, a collector layer, a hole barrier layer, a base layer, an emitter layer, an emitter cap layer, and an ohmic contact layer, all stacked sequentially on a substrate; with the hole barrier layer formed of at least one of AlGaAs, AlGaAsN, AlGaAsP, AlGaAsSb, and InAlGaAs, Aluminum composition being less than 22%, and In, N, P, and Sb compositions being respectively less than or equal to 10%; wherein bandgaps of the hole barrier layer at least comprise a gradually increasing bandgap from the base layer towards the collector layer and the largest bandgap of the hole barrier layer is greater than bandgaps of the base layer and the collector layer.Type: GrantFiled: October 16, 2018Date of Patent: May 12, 2020Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng, Kai-Yu Chen
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Publication number: 20190372310Abstract: A laser diode is provided, including at least a defect blocking layer deposited between the GaAs substrate and the active layer, so that the crystal defects of the GaAs substrate can be blocked or reduced from propagation to the active layer when the epitaxial layer is formed on the GaAs substrate. As such, the crystal quality of the active layer can be improved, thereby improving the reliability and optical property of the laser diode.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Yu-Chung Chin, Chao-Hsing Huang, Van-Truong Dai
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Publication number: 20190115458Abstract: The disclosure provides an HBT structure with bandgap graded hole barrier layer, comprising: a sub-collector layer, a collector layer, a hole barrier layer, a base layer, an emitter layer, an emitter cap layer, and an ohmic contact layer, all stacked sequentially on a substrate; with the hole barrier layer formed of at least one of AlGaAs, AlGaAsN, AlGaAsP, AlGaAsSb, and InAlGaAs, Aluminum composition being less than 22%, and In, N, P, and Sb compositions being respectively less than or equal to 10%; wherein bandgaps of the hole barrier layer at least comprising a gradually increasing bandgap from the base layer towards the collector layer and the largest bandgap of the hole barrier layer being greater than bandgaps of the base layer and the collector layer. The present invention can effectively enhance the overall device performance.Type: ApplicationFiled: October 16, 2018Publication date: April 18, 2019Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng, Kai-Yu Chen
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Patent number: 9853136Abstract: A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, and includes a sub-collector layer, a collector, a base layer, an emitter layer, an emitter cap layer and an ohmic contact layer, which are sequentially formed on the substrate. A tunnel collector layer formed by InGaP or InGaAsP is provided between the collector layer and the base layer. Since an epitaxial process is performed on the substrate from a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, indium and gallium contained in InGaP or InGaAsP are affected by the ordering effect such that InGaP or InGaAsP used in the emitter layer and/or the tunnel collector layer has a higher electron affinity or a smaller bandgap.Type: GrantFiled: November 7, 2014Date of Patent: December 26, 2017Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng
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Publication number: 20160049502Abstract: Provided is a heterojunction bipolar transistor (HBT), including a GaAs substrate; a subcollector layer stacked on the GaAs substrate, wherein a part of or all of the subcollector layer is formed by N-type group III-V semiconductors doped by at least Te and/or Se; a blocking layer structure directly or indirectly stacked on the subcollector layer, and formed by N-type group III-V semiconductors doped by at least group IV elements, a collector layer stacked on the blocking layer structure, and formed by N-type group III-V semiconductors; a base layer stacked on the collector layer, and formed by P-type group III-V semiconductors; an emitter layer stacked on the base layer and formed by N-type group III-V semiconductors; an emitter cap layer stacked on the emitter layer and formed by N-type group III-V semiconductors; and an ohmic contact layer stacked on the emitter cap layer and formed by N-type group III-V semiconductors.Type: ApplicationFiled: May 15, 2015Publication date: February 18, 2016Inventors: Yu-Chung Chin, Chao-Hsing Huang, Hung-Chi Hsiao
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Publication number: 20150255585Abstract: A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, and includes a sub-collector layer, a collector, a base layer, an emitter layer, an emitter cap layer and an ohmic contact layer, which are sequentially formed on the substrate. A tunnel collector layer formed by InGaP or InGaAsP is provided between the collector layer and the base layer. Since an epitaxial process is performed on the substrate from a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, indium and gallium contained in InGaP or InGaAsP are affected by the ordering effect such that InGaP or InGaAsP used in the emitter layer and/or the tunnel collector layer has a higher electron affinity or a smaller bandgap.Type: ApplicationFiled: November 7, 2014Publication date: September 10, 2015Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng
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Patent number: 9130027Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.Type: GrantFiled: July 9, 2014Date of Patent: September 8, 2015Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Yu-Chung Chin, Chao-Hsing Huang
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Patent number: 8994069Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.Type: GrantFiled: June 5, 2013Date of Patent: March 31, 2015Assignee: Visual Photonics Epitaxy Co., Ltd.Inventors: Yu-Chung Chin, Chao-Hsing Huang
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Publication number: 20140361344Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.Type: ApplicationFiled: July 9, 2014Publication date: December 11, 2014Inventors: Yu-Chung Chin, Chao-Hsing Huang
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Publication number: 20140054647Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.Type: ApplicationFiled: June 5, 2013Publication date: February 27, 2014Inventors: Yu-Chung Chin, Chao-Hsing Huang