Patents by Inventor Yu-Chung Chin

Yu-Chung Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120068228
    Abstract: A heterojunction bipolar transistor (HBT) structure with GaPSbAs base is disclosed. The HBT structure generally includes a substrate, a subcollector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and a contact layer laminated from bottom to top sequentially, and optionally may further comprise a buffer layer between the substrate and the subcollector layer. The subcollector layer includes heavily-doped GaAs; the collector layer includes GaAs, InGaP, or AlGaAs; the base layer includes GaPAsSb compound; the emitter layer includes InGaP or AlGaAs; the emitter cap layer includes GaAs; the contact layer includes InGaAs; and the substrate includes semi-insulating GaAs. Since the base having GaPSbAs compound has lower band gap energy, the turn-on voltage of the transistors can be reduced.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Inventors: Yu-Chung Chin, Tsung-Hsin Su
  • Patent number: 7573080
    Abstract: The HBT-based transient suppression device contains a collector layer of a first conduction type, a base layer of a second conduction type, an emitter layer of the first conduction type, stacked in this order sequentially on a top side of a heavily doped substrate of the first conduction type. The doping concentration of the base layer is higher than that of the emitter and collector layers, and that the thickness of the collector layer is less than 300 nm, so that the BVCEO breakdown voltage is reduced below 5V Additionally, the thickness of the base layer is larger than the sum of the thickness of a section of the emitter-base depletion region extending into the base layer and the thickness of a section of the base-collector depletion region extending into the base layer, so that the base layer is not operated in a punch-through condition.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: August 11, 2009
    Assignee: Visual Photonics Epitaxy Co., Ltd.
    Inventors: Chao-Hsing Huang, Yu-Chung Chin
  • Patent number: 7385236
    Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: June 10, 2008
    Assignee: Visual Photonics Epitaxy Co., Ltd.
    Inventors: Yu-Chung Chin, Chao-Hsing Huang, Wei-Chou Wang, Kun-Chuan Lin
  • Patent number: 7224005
    Abstract: A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1-x, 0.0?x?1.0) and/or indium-gallium-arsenic-nitride (InyGa1-yAszN1-z, 0.0?y, z?1.0) in a specific order is used to form the transistor base of a heterojunction bipolar transistor. By controlling the compositions of the materials indium-gallium-arsenic-nitride and gallium-arsenide-antimonide, and by changing the thickness and order of the layers, the new material would possess a specific energy gap, which in turn determines the base-emitter turn-on voltage of the heterojunction bipolar transistor.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: May 29, 2007
    Assignee: Visual Photonics Epitaxy Co., Ltd.
    Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Huai-Tung Yang, Kun-Chuan Lin, Shih-Jane Tsai
  • Publication number: 20070090399
    Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.
    Type: Application
    Filed: October 21, 2005
    Publication date: April 26, 2007
    Inventors: Yu-Chung Chin, Chao-Hsing Huang, Wei-Chou Wang, Kun-Chuan Lin
  • Publication number: 20050051799
    Abstract: A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1?x, 0.0?x?1.0) and/or indium-gallium-arsenic-nitride (InyGa1?yAszN1?z, 0.0?y, z?1.0) in a specific order is used to form the transistor base of a heterojunction bipolar transistor. By controlling the compositions of the materials indium-gallium-arsenic-nitride and gallium-arsenide-antimonide, and by changing the thickness and order of the layers, the new material would possess a specific energy gap, which in turn determines the base-emitter turn-on voltage of the heterojunction bipolar transistor.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 10, 2005
    Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Huai-Tung Yang, Kun-Chuan Lin, Shih-Jane Tsai