Patents by Inventor Yu-Chung Su
Yu-Chung Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230087992Abstract: Photosensitive polymers and their use in photoresists for photolithographic processes are disclosed. The polymers are copolymers, with at least one monomer that includes pendant polycyclic aromatic groups and a second monomer that includes an acidic leaving group (ALG). The polymers have high resistance to etching and high development contrast.Type: ApplicationFiled: March 15, 2022Publication date: March 23, 2023Inventors: Wei-Che Hsieh, Yu-Chung Su, Chia-Ching Chu, Tzu-Yi Wang, Ta-Cheng Lien, Hsin-Chang Lee, Ching-Yu Chang, Yahru Cheng
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Publication number: 20230065897Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, C.W. LEE, Kuan-Wei SU, Chia-Ming PAN
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Publication number: 20230064914Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
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Patent number: 11594645Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.Type: GrantFiled: August 31, 2021Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
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Patent number: 11500179Abstract: A high-resolution imaging lens proofed against high-temperature instability includes a first lens with a negative power, a second lens with a negative power, a third lens with a positive power, a fourth lens with a negative power, a fifth lens with a positive power, and a sixth lens with a positive power. The first to the sixth lenses satisfy conditions of F1<0; 0.8>|F2/F6|>0.6, F2<0, F6>0; ?3>F4/F5>?2, and 2.0<F/#. Each of the first lens, the third lens, the fourth lens, and the fifth lens is made of glass, each of the second lens and the sixth lens is made of plastic.Type: GrantFiled: May 27, 2020Date of Patent: November 15, 2022Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Chung Su, Chun-Cheng Ko
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Publication number: 20220357211Abstract: The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.Type: ApplicationFiled: April 13, 2022Publication date: November 10, 2022Applicant: MEDIATEK INC.Inventors: Min-Hang Hsieh, Jyun-Jia Huang, Chien-Sheng Chao, Ghien-An Shih, Ching-Chung Ko, Yu-Cheng Su, Lin-Chien Chen, Ai-Yun Liu, Chia-Hsin Hu
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Publication number: 20220297254Abstract: A grinding machine tool for reducing hotness of a casing, includes a casing and a drive assembly. The casing is divided into a head and a body; includes casing parts; includes an air inlet provided on the body and an air outlet provided on a side of the head; and forms a motor cover on the head, and the motor cover does not contact the casing parts to form an airflow passage in the casing. The drive assembly includes a circuit board, a motor placed into the motor cover, and an airflow generating member rotating synchronously with the motor. When the airflow generating member rotates, it generates a first heat dissipation airflow passing through the airflow passage and dissipating heat of the circuit board and the head, and a second heat dissipation airflow dissipating heat on a side of the motor facing the airflow generating member.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Ding-Yao CHENG, Chih-Chung LIN, Yu-Fan WEN, Wen-Hsien SU
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Publication number: 20220297255Abstract: An air guider disposed in a grinding machine tool. The grinding machine tool comprises a casing and a motor disposed in the casing. The casing comprises a head for disposing the motor and a body formed with at least one air inlet. The air guider comprises a main body, and an ascending diversion portion integrally formed with the main body, the main body is disposed at a junction between the head and the body, the ascending diversion portion comprises a main guide surface to guide a first heat dissipation airflow entering from the air inlet to flow toward a top of the motor, and two auxiliary guide surfaces respectively disposed on two sides of the main guide surface to generate a second heat dissipation airflow.Type: ApplicationFiled: April 20, 2022Publication date: September 22, 2022Inventors: Ding-Yao CHENG, Chih-Chung LIN, Yu-Fan WEN, Wen-Hsien SU
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Patent number: 11409084Abstract: A lens module includes a first lens having a negative refractive power, a second lens having a positive refractive power, a third lens having a positive refractive power, a fourth lens having a positive refractive power, a fifth lens having a negative refractive power, and an imaging surface, arranged in that sequence from an object side to an image side. The lens module uses infrared light which has a wavelength ranging from 920 to 970 nm, the lens module satisfies the following conditions: 0.0002<|1/F1|<0.01; D/TTL>1.1; CT4/ET4<1.8; F1 denotes a focal length of the first lens, D denotes a diameter of a largest imaging circle of the lens module, TTL denotes a distance between an object side surface of the first lens to the imaging surface, CT4 denotes a central thickness of the fourth lens, ET4 denotes an edge thickness of the fourth lens.Type: GrantFiled: November 25, 2019Date of Patent: August 9, 2022Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Chung Su, Chun-Cheng Ko
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Publication number: 20220238636Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.Type: ApplicationFiled: May 5, 2021Publication date: July 28, 2022Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
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Patent number: 11120995Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.Type: GrantFiled: December 2, 2019Date of Patent: September 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei Hsu, Yu-Chung Su, Chen-Hao Wu, Shen-Nan Lee, Tsung-Ling Tsai, Teng-Chun Tsai
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Patent number: 11094541Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: GrantFiled: July 21, 2020Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Chung Su, Ching-Yu Chang
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Publication number: 20210200092Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.Type: ApplicationFiled: November 13, 2020Publication date: July 1, 2021Inventors: Yu-Chung SU, Tsung-Han KO, Ching-Yu CHANG
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Publication number: 20200379215Abstract: A high-resolution imaging lens proofed against high-temperature instability includes a first lens with a negative power, a second lens with a negative power, a third lens with a positive power, a fourth lens with a negative power, a fifth lens with a positive power, and a sixth lens with a positive power. The first to the sixth lenses satisfy conditions of F1<0; 0.8>|F2/F6|>0.6, F2<0, F6>0; ?3>F4/F5>?2, and 2.0<F/#. Each of the first lens, the third lens, the fourth lens, and the fifth lens is made of glass, each of the second lens and the sixth lens is made of plastic.Type: ApplicationFiled: May 27, 2020Publication date: December 3, 2020Inventors: YU-CHUNG SU, CHUN-CHENG KO
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Publication number: 20200350155Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventors: Yu-Chung Su, Ching-Yu Chang
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Patent number: 10768527Abstract: A method includes providing a photoresist solution that includes a first solvent having a first volume and a second solvent having a second volume, where the first solvent is different from the second solvent and where the first volume is less than the second volume; dispersing the photoresist solution over a substrate to form a film, where the dispersing evaporates a portion of the first solvent and a portion of the second solvent such that a remaining portion of the first solvent is greater than a remaining portion of the second solvent; baking the film; after baking the film, exposing the film to form an exposed film; and developing the exposed film.Type: GrantFiled: August 13, 2018Date of Patent: September 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chung Su, Kuan-Hsin Lo, Yahru Cheng, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 10770293Abstract: In a method of manufacturing a semiconductor device, a photo resist layer is formed over a substrate with underlying structures. The first photo resist layer is exposed to exposure radiation. The exposed first photo resist layer is developed with a developing solution. A planarization layer is formed over the developed photo resist layer. The underlying structures include concave portions, and a part of the concave portions is not filled by the developed first photo resist.Type: GrantFiled: August 20, 2018Date of Patent: September 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chung Su, Yahru Cheng, Ching-Yu Chang
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Patent number: 10755927Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: GrantFiled: December 19, 2018Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Chung Su, Ching-Yu Chang
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Publication number: 20200241261Abstract: A lens module includes a first lens having a negative refractive power, a second lens having a positive refractive power, a third lens having a positive refractive power, a fourth lens having a positive refractive power, a fifth lens having a negative refractive power, and an imaging surface, arranged in that sequence from an object side to an image side. The lens module uses infrared light which has a wavelength ranging from 920 to 970 nm, the lens module satisfies the following conditions: 0.0002<|1/F1|<0.01; D/TTL>1.1; CT4/ET4<1.8; F1 denotes a focal length of the first lens, D denotes a diameter of a largest imaging circle of the lens module, TTL denotes a distance between an object side surface of the first lens to the imaging surface, CT4 denotes a central thickness of the fourth lens, ET4 denotes an edge thickness of the fourth lens.Type: ApplicationFiled: November 25, 2019Publication date: July 30, 2020Inventors: Yu-Chung SU, Chun-Cheng Ko
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Publication number: 20200105538Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.Type: ApplicationFiled: December 2, 2019Publication date: April 2, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei HSU, Yu-Chung SU, Chen-Hao WU, Shen-Nan LEE, Tsung-Ling TSAI, Teng-Chun TSAI