Patents by Inventor Yu-Chung Su
Yu-Chung Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10497574Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.Type: GrantFiled: September 21, 2018Date of Patent: December 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei Hsu, Yu-Chung Su, Chen-Hao Wu, Shen-Nan Lee, Tsung-Ling Tsai, Teng-Chun Tsai
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Publication number: 20190122882Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Inventors: Yu-Chung Su, Ching-Yu Chang
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Publication number: 20190096686Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.Type: ApplicationFiled: September 21, 2018Publication date: March 28, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei HSU, Yu-Chung SU, Chen-Hao WU, Shen-Nan LEE, Tsung-Ling TSAI, Teng-Chun TSAI
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Publication number: 20190067002Abstract: In a method of manufacturing a semiconductor device, a photo resist layer is formed over a substrate with underlying structures. The first photo resist layer is exposed to exposure radiation. The exposed first photo resist layer is developed with a developing solution. A planarization layer is formed over the developed photo resist layer. The underlying structures include concave portions, and a part of the concave portions is not filled by the developed first photo resist.Type: ApplicationFiled: August 20, 2018Publication date: February 28, 2019Inventors: Yu-Chung SU, Joy CHENG, Ching-Yu CHANG
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Patent number: 10163631Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: GrantFiled: September 11, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang
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Patent number: 10082734Abstract: An anti-reflective coating (ARC) composition for use in lithography patterning and a method of using the same is disclosed. In an embodiment, the ARC composition comprises a polymer having a chromophore; an acid labile group (ALG), more than 5% by weight; a thermal acid generator; and an optional crosslinker. The method includes applying the ARC composition over a substrate; crosslinking the polymer to form an ARC layer; cleaving the ALG of the ARC layer to reduce a film density of the ARC layer; forming a resist layer over the ARC layer, patterning the resist layer, and etching the ARC layer. Due to reduced film density, the ARC layer has a high etching rate, thereby preserving the critical dimension (CD) of the resist pattern during the etching process.Type: GrantFiled: February 13, 2015Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang
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Publication number: 20180040617Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.Type: ApplicationFiled: October 13, 2017Publication date: February 8, 2018Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Publication number: 20170372892Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: ApplicationFiled: September 11, 2017Publication date: December 28, 2017Inventors: Yu-Chung Su, Ching-Yu Chang
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Patent number: 9812358Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a recess is formed exposing a plurality of semiconductor fins on a wafer. A dummy contact material is formed in the recess. The dummy contact material contains carbon. The dummy contact material is cured with one or more baking steps. The one or more baking steps harden the dummy contact material. A first portion of the dummy contact material is replaced with an inter-layer dielectric. A second portion of the dummy contact material is replaced with a plurality of contacts. The plurality of contacts are electrically coupled to source/drain regions of the plurality of semiconductor fins.Type: GrantFiled: September 14, 2016Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chun Huang, Ting-Ting Chen, Yu-Chung Su, Ling-Fu Nieh, Pin-Chuan Su, Teng-Chun Tsai, Tai-Chun Huang, Joy Cheng
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Patent number: 9793268Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: GrantFiled: January 24, 2014Date of Patent: October 17, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9761449Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.Type: GrantFiled: August 12, 2014Date of Patent: September 12, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang
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Publication number: 20160260623Abstract: A system for forming a coating comprises applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the first coating after planarizing the top surface. The first coating may be applied over the plurality of topographical features, and may be substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating. A solvent may be applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The first coating may have a planar surface prior to drying the first coating, and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.Type: ApplicationFiled: May 12, 2016Publication date: September 8, 2016Inventors: Wen-Yun Wang, Cheng-Han Wu, Yu-Chung Su, Ching-Yu Chang
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Patent number: 9436086Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.Type: GrantFiled: January 25, 2016Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang
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Publication number: 20160252815Abstract: Methods and materials for making a semiconductor device are described. The method includes forming an out-of-bond-wavelength (OOB)-reduction photoresist over a substrate, forming a floating region adjacent to a top surface of the OOB-reduction photoresist. The floating region has a higher absorbance of the OOB wavelength than a bulk region of the OOB-reduction photoresist that is below the floating region. The method also includes exposing the OOB-reduction photoresist to a radiation beam, wherein an OOB radiation portion of the radiation beam is absorbed in the floating region.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Inventors: Yu-Chung Su, Ching-Yu Chang
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Publication number: 20160238933Abstract: An anti-reflective coating (ARC) composition for use in lithography patterning and a method of using the same is disclosed. In an embodiment, the ARC composition comprises a polymer having a chromophore; an acid labile group (ALG), more than 5% by weight; a thermal acid generator; and an optional crosslinker. The method includes applying the ARC composition over a substrate; crosslinking the polymer to form an ARC layer; cleaving the ALG of the ARC layer to reduce a film density of the ARC layer; forming a resist layer over the ARC layer, patterning the resist layer, and etching the ARC layer. Due to reduced film density, the ARC layer has a high etching rate, thereby preserving the critical dimension (CD) of the resist pattern during the etching process.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: Yu-Chung Su, Ching-Yu Chang
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Patent number: 9362120Abstract: The present disclosure provides a method that includes forming a polymeric material layer on a substrate, wherein the polymeric material layer includes de-crosslinkable crosslink material (DCM); performing a first baking process having a first baking temperature to the polymeric material layer, thereby initiating crosslinking function of the DCM; and performing a second baking process having a second baking temperature to the polymeric material layer, thereby initiating de-crosslinking function of the DCM.Type: GrantFiled: November 10, 2014Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yu-Chung Su
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Publication number: 20160155632Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.Type: ApplicationFiled: January 25, 2016Publication date: June 2, 2016Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang
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Patent number: 9349622Abstract: A method of forming a coating, comprises applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the first coating after planarizing the top surface. The first coating may be applied over the plurality of topographical features, and may be substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating. A solvent may be applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The first coating may have a planar surface prior to drying the first coating, and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.Type: GrantFiled: March 13, 2013Date of Patent: May 24, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yun Wang, Cheng-Han Wu, Yu-Chung Su, Ching-Yu Chang
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Patent number: 9281192Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.Type: GrantFiled: May 13, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kao-Feng Liao, Yu-Ting Yen, Yu-Chung Su
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Patent number: 9245751Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.Type: GrantFiled: October 17, 2013Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang