Abstract: A switching power device comprises a device lead-frame. Gates, Kelvin sources and a drain are formed on the device lead-frame, the gates and the Kelvin sources are arranged at one end of the device lead-frame, and the drain is arranged at the other end of the device lead-frame; and two gates and two Kelvin sources are provided. One end of the device lead-frame is sequentially provided with the gate, the Kelvin source, the Kelvin source and the gate, so as to form a symmetrical pin structure.

Abstract: The present invention provides methods and systems to identify and quantify double-stranded RNA (dsRNA) in a sample. A capture molecule can be immobilized to a solid surface. The solid surface can then be contacted with a sample including the dsRNA, wherein the capture molecule immobilized on the solid surface specifically binds to the dsRNA. The binding response of the dsRNA to the solid surface can then be measured by biolayer interferometry to detect the dsRNA in the sample. The measured binding response can be compared to a standard curve relating binding response to concentration to determine a concentration of the dsRNA in the sample.

Abstract: The present application describes a system with a cost estimation tool for routing a logical edge onto a physical link of a reconfigurable processor and a method of operating such a cost estimation tool. The method comprises a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to the physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor. The method further comprises determining a realized bandwidth consumption of the tentative assignment based on determining an end-to-end bandwidth, which is based on determining whether the end-to-end bandwidth is credit controlled.

Abstract: The present application describes a system with a routing cost estimation tool for routing a logical edge between a logical producer unit and a logical consumer unit onto a reconfigurable processor and a method of operating such a routing cost estimation tool. The method comprises receiving a tentative assignment of the logical producer unit, the logical consumer unit, and the logical edge onto a physical producer unit, a physical consumer unit, and a physical link of the reconfigurable processor, respectively, determining a number of active cycles of the logical edge; determining a number of stage cycles, determining a scaling factor of a realized bandwidth based on a division of the number of active cycles by the number of stage cycles, and determining a realized bandwidth consumption of the tentative assignment based on the scaling factor of the realized bandwidth.

Abstract: A system with a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor is presented as well as a method of operating such a cost estimation tool and a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a cost estimation tool The cost estimation tool may be configured to determine the realized bandwidth consumption of the tentative assignment based on an upper bandwidth limit of the logical edge, an end-to-end bandwidth, a scaling factor of a realized bandwidth, and a congestion estimation of the physical link.

Abstract: The present application describes a system with a cost estimation tool for placing and routing a logical edge onto a reconfigurable processor and a method of operating such a cost estimation tool. The method comprises receiving an operation unit graph comprising the logical edge between a logical producer unit and a logical consumer unit and a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor. The method further comprises determining a realized bandwidth consumption of the tentative assignment based on determining an upper bandwidth limit of the logical edge, determining an end-to-end bandwidth, determining a scaling factor of the realized bandwidth, and determining congestion estimation of the physical link.

Abstract: The invention discloses a method for enhanced denitrification and a device thereof. The device comprises an anoxic tank, an aerobic tank and a carbon source booster connected in sequence, and an output end of the carbon source booster is then connected with the anoxic tank; a plurality of membrane contactors are fixed inside the carbon source booster, the membrane contactor is in a hollow structure, and there is a gap between the membrane contactors and a shell of the carbon source booster. By adopting the device, macromolecular carbon source can be added and hydrolyzed into volatile fatty acids by using the hydrolytic fermentation bacteria existing in the gap between the carbon source booster and the membrane contactors, which then penetrates into the hollow part of the membrane contactors through membrane diffusion, as a small molecular carbon source that can be effectively used by denitrifying bacteria to promote the denitrification process.

Abstract: The present inventions provide a concise panel of chromatography-based stability-indicating methods for evaluating in vitro transcribed (IVT) mRNA under various conditions, including varying types and degrees of stress conditions, as part of a forced degradation study. The inventions also provide that addition of EDTA to the mRNAs prior to heat exposure reduces the extent of mRNA degradation, that the transcripts are fragmenting via a divalent metal-ion mediated pathway. The inventions also provide the application of the methods to evaluate the critical quality attributes (CQAs) of mRNAs as well as to detect intrinsic process and product related impurities.

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.

Abstract: The inventions provide methods for characterizing messenger RNAs (mRNA) and polyadenylation on mRNAs. The disclosed inventions are developed for characterizing mRNA and poly(A) tail length on mRNA samples. These inventions can be used in release testing of mRNA drug substrate (DS) or drug product (DP), and can provide direct read-out of mRNA integrity and poly(A) tail length. The inventions further provide methods of analyzing the condition of mRNAs in samples. Characterized mRNA samples obtained by all of the inventive methods also are part of the inventions disclosed herein.

Abstract: The invention discloses a method for enhanced denitrification and a device thereof. The device comprises an anoxic tank, an aerobic tank and a carbon source booster connected in sequence, and an output end of the carbon source booster is then connected with the anoxic tank; a plurality of membrane contactors are fixed inside the carbon source booster, the membrane contactor is in a hollow structure, and there is a gap between the membrane contactors and a shell of the carbon source booster. By adopting the device, macromolecular carbon source can be added and hydrolyzed into volatile fatty acids by using the hydrolytic fermentation bacteria existing in the gap between the carbon source booster and the membrane contactors, which then penetrates into the hollow part of the membrane contactors through membrane diffusion, as a small molecular carbon source that can be effectively used by denitrifying bacteria to promote the denitrification process.

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph. The operation unit graph may include first and second logical units that perform first and second data operations and have first and second ports, respectively, coupled by a logical edge, on a reconfigurable processor. The method includes receiving the operation unit graph, determining first and second upper bandwidth limits of the first and second ports, respectively, determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits, determining a timing group for the logical edge, and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

Abstract: A system with a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor is presented as well as a method of operating such a cost estimation tool and a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a cost estimation tool The cost estimation tool may be configured to determine the realized bandwidth consumption of the tentative assignment based on an upper bandwidth limit of the logical edge, an end-to-end bandwidth, a scaling factor of a realized bandwidth, and a congestion estimation of the physical link.

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.

Abstract: A method for training a model, a method for controlling an object, an apparatus, a medium, and a device. The method includes acquiring an interaction sequence generated by an interaction between a first virtual object and a second virtual object in a virtual environment; acquiring a training reward weight parameter corresponding to each interaction sequence; determining a target return value corresponding to each of the sampled data, according to the training reward weight parameter corresponding to the interaction sequence and the return value in the interaction sequence; determining a target loss of the training deep reinforcement learning model, according to an action-value predicted value determined based on a state feature and a decision action of each of the sampled data and the target return value corresponding to the sampled data; and training the training deep reinforcement learning model based on the target loss.

Abstract: The present disclosure discloses an injection molding method for fabricating a transparent device, and belongs to the technical field of material processing. The method comprises: preparing a nano-microsphere structural polymer material from a long-chain polymer material; obtaining a glass transition temperature and a viscous flow transition temperature of the nano-microsphere structural polymer material; obtaining a processing temperature of the nano-microsphere structural polymer material according to the glass transition temperature and the viscous flow transition temperature; drying the nano-microsphere structural polymer material; plasticizing the dried nano-microsphere structural polymer material according to the processing temperature; filling the plasticized nano-microsphere structural polymer material; cooling the filled nano-microsphere structural polymer material; and demolding the cooled nano-microsphere structural polymer material to form a transparent device.

Abstract: A training method for a neural network includes determining first disassembly paths of a plurality of first molecules, and obtaining a first cost dictionary based on the first disassembly paths of the first molecules. The method also includes determining molecular expression information of second molecules based on the first disassembly paths of the first molecules, and determining a plurality of third molecules from the second molecules, each of the third molecules representing a class of the second molecules. The method further includes obtaining a second cost dictionary based on second disassembly paths of the third molecules, and performing training based on the first cost dictionary and the second cost dictionary to obtain a target neural network. The target neural network being configured to output cost value information corresponding to a target molecule according to input molecular expression information of the target molecule.

Abstract: A switching power device comprises a device lead-frame. Gates, Kelvin sources and a drain are formed on the device lead-frame, the gates and the Kelvin sources are arranged at one end of the device lead-frame, and the drain is arranged at the other end of the device lead-frame; and two gates and two Kelvin sources are provided. One end of the device lead-frame is sequentially provided with the gate, the Kelvin source, the Kelvin source and the gate, so as to form a symmetrical pin structure.