Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.

Abstract: A display panel includes pixel circuits, first shift register(s), second shift register(s), third shift register(s), and fourth shift register(s). A pixel circuit includes a driving transistor, a bias sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a leakage prevention sub-circuit, a reset sub-circuit, and a light-emission control sub-circuit. The bias sub-circuit is electrically connected to a first shift register, which transmits a first scanning signal to the bias sub-circuit. The data writing and compensation sub-circuits are electrically connected to a second shift register, which transmits a second scanning signal to the data writing and compensation sub-circuits. The leakage prevention sub-circuit is electrically connected to a third shift register, which transmits a third scanning signal to the leakage prevention sub-circuit.

Abstract: A wireless charging device is disclosed. At least one floating charging component is arranged in the wireless charging device, the floating charging component comprises a supporting plate, a power transmission coil, and a magnetic element, the top wall of a housing is provided with at least one mounting hole, and the floating charging component is movably arranged in the mounting hole, so that when the device to be charged is placed on a bearing surface of the top wall, the magnetic element is able to attract the device to be charged so that the outer surface of the supporting plate contacts with the device to be charged, so that ensures that the power transmission coil and the device to be charged be aligned with each other and the distance between them is small, thereby ensuring the wireless charging rate.

Abstract: Provided are a display panel, a display apparatus and a method for driving the display panel. The display panel includes: multiple gate lines; and multiple shift register units, a target shift register unit of the shift register units includes: a frame trigger selecting circuit and a gate driving circuit; the frame trigger selecting circuit is coupled to a frame trigger input terminal and frame starting signal terminals corresponding to N cascade groups, and outputs, in response to an nth turn-on signal of N turn-on signals corresponding to an nth cascade group, a starting signal input to the frame trigger input terminal to a frame starting signal terminal corresponding to the nth cascade group; 1?n?N, and n is an integer; the nth cascade group scans the gate lines coupled thereto line by line after the frame starting signal terminal corresponding thereto receives the starting signal.

Abstract: A shift register unit and a driving method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes: an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; wherein the input circuit is connected to an input terminal; the first control circuit is connected to the first node, a second node, and a first clock signal terminal; the output circuit is connected to an output terminal; the output noise reduction circuit is connected to the output terminal; and the reset circuit is connected to a total reset terminal and a first voltage terminal, wherein the total reset signal is an invalid level in a first operation stage, and the total reset signal includes at least one period of valid level in a second operation stage.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

Abstract: Provided are a display substrate, a display panel, and a display device. The display substrate includes a base substrate, pixel circuits, groups of data lines, and first power lines. At least one column of pixel circuits is electrically connected to at least one group of data lines and includes first and second pixel circuits alternately arranged in the second direction. The at least one group of data lines includes first and second data lines. For the at least one column of pixel circuits, input transistors of first and second pixel circuits are electrically connected to first and second data lines, respectively. In the first direction, the first data line, the first power line and the second data line are arranged in sequence, and input transistors of first and second pixel circuits are respectively located on a side of the first power line close to the first and second data line.

Abstract: A pixel circuit, a pixel driving method, and a display device.

Abstract: A display panel and a display device are provided. The display panel includes a base substrate and a pixel driving circuit provided on a side of the base substrate, and the pixel driving circuit includes a driving transistor, ninth transistor, eighth transistor, first transistor and second transistor. A first electrode of the ninth transistor is connected to a third initial signal line and a second electrode of the ninth transistor is connected to a first electrode of the driving transistor. A first electrode of the eighth transistor is connected to a gate electrode of the driving transistor. A first electrode of the first transistor is connected to a first initial signal line and a second electrode of the first transistor is connected to a second electrode of the eighth transistor. A first electrode of the second transistor is connected to the second electrode of the eighth transistor and a second electrode of the second transistor is connected to a second electrode of the driving transistor.

Abstract: A vehicle rear seat entertainment integration module is provided, the vehicle rear seat entertainment integration module has a display and a multi-functional remote controller, wherein the top of the display has an accommodating space for storing the multi-functional remote controller to solve the problem of losing the multifunctional remote controller due to the lack of storage space. In addition, the multifunctional remote controller may be used as a game handle to enhance the entertainment value of the rear seat of the vehicle.

Abstract: An audio device and a control method thereof are provided. The audio device includes a first switch, a controller, and multiple audio switches. The first switch is turned on or cut off according to whether an audio jack is on a setting position. A first end of the first switch receives a bias voltage. The controller is coupled to the first switch, and generates control signals according to a turned-on or cut-off status of the first switch. The audio switches are respectively coupled between transmission paths of multiple audio signals. The audio switches are turned on or cut off according to the control signals or a voltage on a second end of the first switch.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.

Abstract: A quick-release structure and a vehicle rear seat display module using the same are provided. The quick-release structure includes a display docking piece, a fixing bracket docking piece, and a connecting hinge. The display docking piece and the fixing bracket docking piece may move relatively through the connecting hinge, so that a display fixed on the quick-release structure may be adjusted in pitch angle. In addition, the display docking piece also has a rotating mechanism, which makes a display rotate from a horizontal direction to a vertical direction.

Abstract: The invention discloses a method for synthesizing 1,7-naphthyridine derivatives, which relates to the technical field of synthesizing pharmaceutical intermediates and organic chemical intermediates, wherein the method includes: (1) 2-chloro-3-amino-pyridine being used as Compound I as a starting material, and protecting an amino group to prepare Compound II; (2) the Compound II reacting with an aldehydation reagent under alkaline conditions to obtain Compound III; (3) cyclizing the Compound III with acrylate compounds under the action of Lewis acid to prepare compound IV.

Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a storage capacitor (Cst) having a first capacitor electrode (Ce1) and a second capacitor electrode (Ce2); a driving transistor (Td) configured to generate a driving current; and a switch (SW) configured to control connection or disconnection between a gate electrode of the driving transistor (Td) and the first capacitor electrode (Ce1).

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first initialization circuit and a reset circuit; the first initialization circuit configured to write a first initial voltage into the first end of the driving circuit under the control of an initialization control signal; the reset circuit is configured to write a reset voltage into the second end of the driving circuit or the first end of the driving circuit under the control of a second scan signal; the driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of a control end of the driving circuit.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.