Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

Abstract: A generation method and generation apparatus of a medical report are provided. In the method, the writing style is analyzed from multiple historical texts, where the writing style includes multiple common words in the historical text and the contextual relationships that connect those common words; the medical data is converted into draft text that conforms to the template text, where the template text is a report that conforms to a preset style; and by using the draft text and writing style as input data of the language model, an output report that conforms to the writing style is generated, where the language model selects sentences that conform to the writing style.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A display device is provided. The display device includes a substrate, a driving transistor, a first insulation layer, a first electrode and a second insulation layer. The driving transistor is disposed on the substrate and includes a gate electrode, and the gate electrode projects a first projection profile on the substrate. The first insulation layer is disposed on the driving transistor. The first electrode is disposed on the first insulation layer, and projects a second projection profile on the substrate. The second insulation layer is disposed on the first electrode and the first insulation layer. The second insulation layer has an opening, the opening exposes a portion of the first electrode, and the opening projects a third projection profile on the substrate.

Abstract: A polypeptide and a use thereof in regulating blood glucose level and/or reducing fat are disclosed. The amino acid sequence of the polypeptide includes the sequence of SEQ ID No.: 1, the sequence of SEQ ID No.: 2, the sequence of SEQ ID No.: 3, the sequence of SEQ ID No.: 4, or a sequence obtained by modifying at least one amino acid in any of the aforesaid sequences. The polypeptide disclosed herein has the physiological activity to enhance fat metabolism and regulate blood glucose level. Therefore, administering an effective amount of the polypeptide, or a composition containing the polypeptide, to an individual can effectively produce the effect of treating or preventing a disease related to blood glucose imbalance or to imbalance in fat metabolism.

Abstract: A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: Provided are a display substrate, a display panel, and a display device. The display substrate includes a base substrate, pixel circuits, groups of data lines, and first power lines. At least one column of pixel circuits is electrically connected to at least one group of data lines and includes first and second pixel circuits alternately arranged in the second direction. The at least one group of data lines includes first and second data lines. For the at least one column of pixel circuits, input transistors of first and second pixel circuits are electrically connected to first and second data lines, respectively. In the first direction, the first data line, the first power line and the second data line are arranged in sequence, and input transistors of first and second pixel circuits are respectively located on a side of the first power line close to the first and second data line.

Abstract: A display panel and a display device are provided. The display panel has a display area and a binding area. The display panel includes a color film substrate and an array substrate, wherein the color film substrate includes a near-field communication antenna, the near-field communication antenna includes a coil structure, and the coil structure is at least partially located in the display area; and the array substrate includes a first base substrate, a channel region and a non-channel region, wherein an orthographic projection of the coil structure on the first base substrate is located within an orthographic projection of the non-channel region on the first base substrate.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: Systems and methods for a convertible car seat in accordance with embodiments of the invention are disclosed. In one embodiment, a convertible car seat includes an outer shell having a seat portion and a back portion, a base assembly having a mechanism for mounting the car seat, an adjustable headrest, and an adjustment mechanism.

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Abstract: A light module includes a light guide plate, a first light source and a second light source. The light guide plate has an inner light emitting surface, an outer light emitting surface opposite to the inner light emitting surface, and a light incident surface connecting the inner light emitting surface and the outer light emitting surface. The first light source is disposed on the light incident surface and located between the inner light emitting surface and the outer light emitting surface, and the first light source emits light of a first color temperature. The second light source is disposed on the light incident surface and located between the first light source and the inner light emitting surface, and the second light source emits light of a second color temperature, and the difference between the first color temperature and the second color temperature is greater than 2000K.

Abstract: A scan circuit is provided. The scan circuit includes a random addressing circuit and a plurality of scan units. The random addressing circuit is configured to receive 2k number of control signals, and is configured to select at least one scan unit for outputting signals based on the 2k number of control signals. The plurality of scan units includes a plurality of scan unit groups. A respective scan unit group of the plurality of scan unit groups includes m number of scan units, and is configured to receive n number of clock signals. A respective scan unit of the m number of scan units in the respective scan unit group is configured to receive n? number of clock signals, n?<n, n? and n being positive integers. At least two scan units of the m number of scan units are configured to receive different combinations of clock signals.