Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a multi-layer stack disposed on a substrate and having a plurality of conductive layers interleaved between a plurality of dielectric layers. A channel layer is arranged along a side of the multi-layer stack. A ferroelectric material is arranged between the channel layer and the side of the multi-layer stack. A plurality of oxygen scavenging layers are respectively arranged between the ferroelectric material and sidewalls of the plurality of conductive layers. The plurality of oxygen scavenger layers are entirely confined below the plurality of dielectric layers.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Abstract: A semiconductor structure includes a gate, a self-aligned contact (SAC) layer that is disposed on the gate and that has a seam at a top surface of the SAC layer, a gate spacer that is formed on a sidewall of the gate, and a metal contact that is disposed adjacent to the gate spacer and that is spaced apart from the gate by the gate spacer. The SAC layer includes a filler that seals the seam in the SAC layer, and a top surface of the filler is coplanar with a top surface of the gate spacer and a top surface of the metal contact.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Abstract: A testing apparatus includes a circuit board, a probe station and a probe array. The circuit board includes a plurality of contacts. The probe station includes a platform located on the circuit board and used for carrying a device under test (DUT), and a plurality of probe holes formed on the platform and arranged in an array. The probe array includes a plurality of telescopic probes respectively linearly inserted into the probe holes. One end of each of the telescopic probes is contacted with one of the contacts, and the other end thereof is contacted with one of solder balls of the DUT. Each of the probe holes includes an elongated groove penetrating through the platform. Each of the telescopic probes is provided with a fin protruding outwardly and inserting into the elongated groove.

Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate, and a first display region and a second display region that are located on the base substrate, where the first display region includes a plurality of first sub-pixels and a plurality of transparent regions, the second display region includes a plurality of second sub-pixels, and a distribution density of the first sub-pixels is smaller that of the second sub-pixels; and an area occupied by the first sub-pixels is smaller than that occupied by the second sub-pixels.

Abstract: A vehicle device is provided, which includes a light-emitting unit and a screen separately disposed on a vehicle body. In a first state, the screen is stored in a first portion. In a second state, at least a part of the screen is stretched out of the first portion, and the screen has a vertical length of H, which satisfies: H=[(L?d)*tan(?d)]+[(L?d)*tan(?u)] and H<Hv. L is a first horizontal distance between a viewing point and a first barrier element. d is a second horizontal distance between the screen and the first barrier element in the second state. ?d is a viewing angle below the horizontal plane when observes from the viewing point to the screen, with ?d?70 degrees. ?u is a viewing angle above the horizontal plane when observes from the viewing point to the screen. Hv is a height of the space inside the vehicle.

Abstract: The present disclosure describes a method that includes scanning a circuit layout and identifying layout regions of the circuit layout. The method further includes placing unit cells in a layout region of the layout regions and forming a micro pad structure at a border of a unit cell of the unit cells. The micro pad structure includes interconnect structures that are electrically connected to the unit cell.

Abstract: A power supply has a housing, a circuit board, a wire, and a wire securing assembly. The wire securing assembly has a base plate and a securing structure. The securing structure has a first plate and a second plate. A side edge of the first plate is connected to the base plate. The second plate is spaced apart from the first plate. The wire is mounted through and between the first plate and the second plate. The wire securing assembly is modified from the current insulating part, in which the original side plate extends and forms an additional part, or a bent structure is added on the original side plate, and thus the additional structures become the securing structure. Thus, the wire is prevented from moving under vibration or external force and contacting the blades of the fan, or keeps in a position in compliance with safety requirements.

Abstract: A baffle structure includes a main body, a first board, and a second board. The first board has a first sliding groove and a second sliding groove. The main body is slidable along the first sliding groove, making the first board movable between a first height position and a second height position below the first height position. The second board is located on the first board. The second board is slidable along the second sliding groove. The second board is movable to a third height position below the second height position. By moving the first board and the second board to the first height position, the second height position, and the third height position, the baffle structure can be quickly switched between a transportation mode, a foot protection mode, and a wind blocking mode. A rack and a server system using the baffle structure are also disclosed.

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: An electronic device includes a substrate structure, an insulating layer, a semiconductor unit and a first electromagnetic signal adjusting unit. The insulating layer is disposed on the substrate structure and has a recess. The semiconductor unit is disposed in the recess. The first electromagnetic signal adjusting unit is disposed on the insulating layer and configured for adjusting an electromagnetic signal, wherein the first electromagnetic signal adjusting unit is overlapped with the semiconductor unit. In a top view of the electronic device, a first distance is between a defined center of the recess and a defined center of the semiconductor unit, a second distance is between a defined center of the first electromagnetic signal adjusting unit and the defined center of the semiconductor unit, and the first distance is greater than 0 and the second distance is less than or equal to the first distance.

Abstract: A method that includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block has a corner, adding first patterns along a first edge of the corner, adding second patterns along a second edge of the corner, moving a first column of the first patterns closest to the second edge horizontally toward the second edge, moving a second column of second patterns closest to the second edge horizontally toward the second edge, extending lengths of the first and second patterns in the first and second columns, and outputting a pattern layout in a computer-readable format, where the pattern layout includes the first patterns and the second patterns.

Abstract: A driving device includes a first current source, a second current source, a first common-mode current elimination (CMCE) circuit, a second common-mode current elimination (CMCE) circuit, a current-to-voltage converter, and a first comparator. The current sources provide constant currents. The current-to-voltage converter includes a first current mirror and a second current mirror. The control terminal of the first current mirror is coupled to the second CMCE circuit. The control terminal of the second current mirror is coupled to the first CMCE circuit. The first current mirror and the second current mirror receive the constant currents, common-mode currents, and differential currents, thereby controlling the first CMCE circuit and the second CMCE circuit to generate a voltage difference that excludes a common-mode voltage corresponding to the common-mode currents. The first comparator receives the voltage difference to drive a field-effect transistor.

Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.