Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.

Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.

Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A display device includes a touch panel, an optical adhesive layer, and a front light module that includes a light source and a light guide plate (LGP) including multiple microstructures recessed into the LGP from a first surface of the LGP to form voids. The optical adhesive layer is adhered between the touch panel and a first surface of the LGP. A surface of the optical adhesive layer facing the LGP is in contact with the first surface of the LGP in multiple first regions, and a surface of the optical adhesive layer facing the LGP and the plurality of microstructures being overlapped in multiple second regions. A maximum vertical distance between each void and the first surface is a first depth. A vertical distance between the first regions and the second regions is 0 to 0.7 times the first depth.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A voice coil motor held immobile by magnetic attraction when not in use for photography purposes includes a base, a magnet fixed thereto, a carrier, a magnetic member, and a coil. The magnetic member is fixed to the carrier and is attracted by a permanent magnetic field (first MF) of the magnet on the base. The coil is fixed to the carrier and the magnetic member. When the voice coil motor is powered on, the coil generates a second magnetic field (second MF) opposing the first MF. The second MF reduces or eliminates the attractive force of the first MF of the magnet, to separate the carrier and its fittings and allow them to work freely. A lens module and an electronic device are further provided.

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: The disclosure relates to processing application programming interface (API) requests. Embodiments include receiving, at an API wrapper, from a first caller, a first call to an API and sending the first call to the API. Embodiments include receiving, by the API wrapper, from one or more second callers, a second one or more calls to the API prior to receiving a response from the API to the first call. Embodiments include receiving, by the API wrapper, the response from the API to the first call and responding to the first call from the first caller with the response from the API to the first call. Embodiments include responding, by the API wrapper, to the second one or more calls from the one or more second callers with the response from the API to the first call without sending the second one or more calls to the API.

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: The present disclosure relates to a pixel drive circuit, a driving method thereof, and a display panel, which relates to the field of display technology. The source, drain and gate of the drive transistor of the pixel drive circuit are respectively connected to the first node, the second node and the third node. The storage capacitor is connected to the third node. The first control unit is used for enabling a path between the second node and the fourth node in response to the first control signal. The second control unit is used for outputting the first power supply voltage to the first node in response to the light-emitting signal. The threshold compensation transistor is used for enabling a path between the second node and the third node in response to the second control signal. The material of the active region is a metal oxide semiconductor.

Abstract: A power chip package and a power module are provided. The power chip package includes a metal cover, a power chip, and a thermal conductive material. A recess is formed on a side surface of the metal cover. The power chip is bonded on the metal cover and is located in the recess. The thermal conductive material fills the recess and surrounds the power chip. At least one first electrode of the power chip is exposed out of the thermal conductive material. The power module includes a circuit board, plural power chip packages and a polymeric resin. The power chip packages are disposed on the circuit board. The polymeric resin packages the power chip packages on the circuit board.

Abstract: An antibody detection test strip of integrating primary screening and diagnosis of sheep brucellosis includes: a test strip 1 of primary screening and a test strip 2 of diagnosis, each including a PVC base plate, a sample pad, a colloidal gold labeled pad, a nitrocellulose membrane and an absorbent pad. For the test strip 1, the colloidal gold labeled pad is coated with colloidal gold labeled Brucella LPS and mouse anti Flag monoclonal antibody, and test and control lines are respectively coated with a Brucella monoclonal antibody M4 and a sheep anti-mouse IgG antibody. For the test strip 2, the colloidal gold labeled pad, and test and control lines are respectively coated with a colloidal gold labeled Brucella LPS, a rabbit anti-sheep IgG antibody and a Brucella monoclonal antibody M4. When in use, a serum is dripped into its sample-loading hole, and brucellosis determination can be made on site according to results presented by the test strips 1 and 2.

Abstract: An antibody detection test strip of integrating primary screening and diagnosis of bovine brucellosis is provided. The antibody detection test strip includes a primary screening test strip and a diagnosis test strip. Each of the primary screening test strip and the diagnosis test strip is composed of a polyvinyl chloride base plate, a sample pad, a colloidal gold labeled pad, a nitrocellulose membrane and an absorbent pad. The sample pad of the primary screening test strip and the sample pad of the diagnosis test strip are connected, and a connection is formed with a sample-loading hole. When in use, a serum to be tested as a sample is dripped into the sample-loading hole, and according to results presented by the primary screening test strip and the diagnosis test strip, brucellosis negative, positive or suspicious determination for the sample can be quickly made on site.

Abstract: A performing device of an impulse-like gesture recognition system executes an impulse-like gesture recognition method. A performing procedure of the impulse-like gesture recognition method includes steps of: receiving a sensing signal from a sensing unit; determining a prediction with at least one impulse-like label according to the sensing frames by a deep learning-based model; and classifying at least one gesture event according to the prediction. The gesture event is classified to determine the motion of the user. Since the at least one impulse-like label is used to label at least one detection score of the deep learning-based model, the detection score is non-decreasing, reaction time of the at least one gesture event for an incoming gesture is fast, rapid consecutive gestures are easily decomposed, and an expensive post-processing is not needed.

Abstract: The present disclosure provides a tray assembly having a dual-structure. The tray assembly comprises an upper tray and a lower tray. The lower tray is capable of being easily disengaged from the upper tray by use of a dovetail joint that allows the lower tray to slidably move relative to the upper tray. The tray assembly also utilizes magnets to reduce the use of mechanical joints. The combination of the magnets together with the dovetail joint provides a quick and efficient way of sliding the lower tray in and out from the upper tray. The lower tray having a collection region collects any external, foreign materials generated during a chemical mechanical polishing/planarizing process. After the cleaning process, the lower tray can be slid back into the upper tray for use.