Patents by Inventor Yu-Gwang Jeong

Yu-Gwang Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11594639
    Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Su Lee, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang, Dae Ho Kim, Jae Neung Kim, Myoung Geun Cha, Sang Gap Kim, Yu-Gwang Jeong
  • Publication number: 20230054453
    Abstract: A display device includes a first electrode and a second electrode, a first insulating layer covering the first electrode and the second electrode, light emitting elements disposed on the first insulating layer, a first connection electrode disposed on the first electrode and contacting an end of each of the light emitting elements, a second connection electrode spaced apart from the first connection electrode and disposed on the second electrode and contacting another end of each of the light emitting elements, a second insulating layer disposed on the first insulating layer and at least partially covering the first connection electrode and the second connection electrode, and a third insulating layer disposed on part of the second insulating layer, wherein the second insulating layer comprises an opening overlapping a part between the first connection electrode and the second connection electrode spaced apart from each other.
    Type: Application
    Filed: May 3, 2022
    Publication date: February 23, 2023
    Applicant: Samsung Display Co., LTD.
    Inventors: Su Bin BAE, Yun Jong YEO, Da Woon JUNG, Yu Gwang JEONG
  • Patent number: 11574973
    Abstract: A method of manufacturing a display panel includes providing an insulating substrate that includes a hole area, a display area that surrounds the hole area, and a peripheral area adjacent to the display area, forming a semiconductor pattern in the display area, forming an insulating layer, forming contact holes in the insulating layer that expose portions of the semiconductor pattern, and forming a module hole by etching a portion of the insulating layer and a portion of the insulating substrate that overlap the hole area.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 7, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yu-Gwang Jeong, Taewook Kang, Wooyong Sung
  • Publication number: 20220415932
    Abstract: A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 29, 2022
    Inventors: Sungwon CHO, Yu-Gwang JEONG, Daewon CHOI, Seon-Il KIM, Subin BAE, Yun Jong YEO
  • Publication number: 20220384549
    Abstract: A method of manufacturing a display panel includes providing an insulating substrate that includes a hole area, a display area that surrounds the hole area, and a peripheral area adjacent to the display area, forming a semiconductor pattern in the display area, forming an insulating layer, forming contact holes in the insulating layer that expose portions of the semiconductor pattern, and forming a module hole by etching a portion of the insulating layer and a portion of the insulating substrate that overlap the hole area.
    Type: Application
    Filed: August 3, 2022
    Publication date: December 1, 2022
    Inventors: Yu-Gwang JEONG, Taewook KANG, Wooyong SUNG
  • Patent number: 11462574
    Abstract: A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sungwon Cho, Yu-Gwang Jeong, Daewon Choi, Seon-Il Kim, Subin Bae, Yun Jong Yeo
  • Patent number: 11422654
    Abstract: An electronic device includes a display panel including a plurality of pixels. A first detection insulating layer is disposed on the display panel. A first conductive pattern is disposed on the first detection insulating layer. A compensation pattern is disposed on the first detection insulating layer. A second detection insulating layer is disposed on the first detection insulating layer and covers the first detection insulating layer, the compensation pattern and the first conductive pattern. A second conductive pattern is disposed on the second detection insulating layer. The first conductive pattern includes a lower surface in contact with the first detection insulating layer. An upper surface faces the lower surface and contacts the second detection insulating layer. Lateral side surfaces extend between the lower surface and the upper surface. The compensation pattern contacts the lateral side surfaces of the first conductive pattern.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Daewon Choi, Yunjong Yeo, Yu-Gwang Jeong, Sungwon Cho
  • Patent number: 11417636
    Abstract: A display device includes a substrate and a display element layer on the substrate. The display element layer includes: first and second electrodes extending along a first direction and spaced apart from each other in a second direction; and light emitting elements electrically connected to the first and second electrodes. The first electrode has a first convex portion convex toward the second electrode and a first concave portion concave in a direction away from the second electrode, and the second electrode has a second convex portion convex toward the first electrode and a second concave portion concave in a direction away from the first electrode. The light emitting elements includes a first and second light emitting elements, respectively close to the first concave portion and the second concave portion based on an imaginary extension line extending in the first direction between the first electrode and the second electrode.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Bin Bae, Seon Il Kim, Sung Won Cho, Yun Jong Yeo, Yu Gwang Jeong
  • Publication number: 20220229322
    Abstract: A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 ? to about 300 ?, and a thickness of the main conductive layer is in a range of about 1,000 ? to about 20,000 ?.
    Type: Application
    Filed: April 5, 2022
    Publication date: July 21, 2022
    Applicant: Samsung Display Co., LTD.
    Inventors: Seon-Il KIM, Sung Won CHO, Sang Gab KIM, Su Bin BAE, Yu-Gwang JEONG, Dae Won CHOI
  • Patent number: 11320712
    Abstract: A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 ? to about 300 ?, and a thickness of the main conductive layer is in a range of about 1,000 ? to about 20,000 ?.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seon-Il Kim, Sung Won Cho, Sang Gab Kim, Su Bin Bae, Yu-Gwang Jeong, Dae Won Choi
  • Patent number: 11276580
    Abstract: A connecting structure of a conductive layer includes a first conductive layer, a first insulating layer disposed on the first conductive layer and including a first opening overlapping the first conductive layer, a connecting conductor disposed on the first insulating layer and connected to the first conductive layer through the first opening, an insulator island disposed on the connecting conductor, a second insulating layer disposed on the first insulating layer and including a second opening overlapping the connecting conductor and the insulator island, and a second conductive layer disposed on the second insulating layer and connected to a connecting electrode through the second opening. A sum of a thickness of the first insulating layer and a thickness of the second insulating layer is greater than or equal to 1 ?m, and each of the thicknesses of the first and second insulating layers is less than 1 ?m.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Su Bin Bae, Yu-Gwang Jeong, Shin Il Choi, Sang Gab Kim, Joon Geol Lee
  • Publication number: 20220068979
    Abstract: A method for etching an insulating layer includes: sequentially forming a first gate insulating layer, an amorphous silicon layer, a first interlayer insulating layer, and a second interlayer insulating layer on a substrate; applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process; first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas used in the first etching.
    Type: Application
    Filed: March 25, 2021
    Publication date: March 3, 2022
    Inventors: Dae Soo KIM, Yu-Gwang JEONG, Sung Won CHO
  • Publication number: 20220059630
    Abstract: A display device includes a substrate, an active pattern disposed on the substrate, a gate electrode overlapping the active pattern, an inorganic insulation layer covering the active pattern, a source metal pattern and an etch-delaying pattern. The source metal pattern includes a first portion that is disposed on the inorganic insulation layer, and a second portion that passes through the inorganic insulation layer and electrically contacts the active pattern. The etch-delaying pattern is disposed between the active pattern and the first portion of the source metal pattern, contacts the second portion of the source metal pattern, and includes a different material from the inorganic insulation layer.
    Type: Application
    Filed: May 11, 2021
    Publication date: February 24, 2022
    Inventors: SUNGWON CHO, YU-GWANG JEONG, DAESOO KIM
  • Publication number: 20220050542
    Abstract: An electronic device includes a display panel including a plurality of pixels. A first detection insulating layer is disposed on the display panel. A first conductive pattern is disposed on the first detection insulating layer. A compensation pattern is disposed on the first detection insulating layer. A second detection insulating layer is disposed on the first detection insulating layer and covers the first detection insulating layer, the compensation pattern and the first conductive pattern. A second conductive pattern is disposed on the second detection insulating layer. The first conductive pattern includes a lower surface in contact with the first detection insulating layer. An upper surface faces the lower surface and contacts the second detection insulating layer. Lateral side surfaces extend between the lower surface and the upper surface. The compensation pattern contacts the lateral side surfaces of the first conductive pattern.
    Type: Application
    Filed: June 10, 2021
    Publication date: February 17, 2022
    Inventors: DAEWON CHOI, YUNJONG YEO, YU-GWANG JEONG, SUNGWON CHO
  • Publication number: 20220005799
    Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Su Bin BAE, Yu Gwang JEONG, Shin Il CHOI, Joon Geol LEE, Sang Gab KIM
  • Patent number: 11211534
    Abstract: A display device includes: a pixel circuit disposed on a base layer; an insulating layer disposed on the base layer covering the pixel circuit; a first electrode disposed on the insulating layer; a second electrode disposed on the insulating layer, the second electrode being spaced apart from the first electrode in a first direction; a light-emitting element disposed between the first electrode and the second electrode; a connection electrode connecting the first electrode and the light-emitting element and connecting the second electrode and the light-emitting element; a first auxiliary insulating layer disposed on the light-emitting element; and a second auxiliary insulating layer disposed on the first auxiliary insulating layer. The second auxiliary insulating layer includes a first insulating portion overlapped with the first auxiliary insulating layer, and a second insulating portion disposed outwardly from the first insulating portion and not overlapping the first auxiliary insulating layer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Subin Bae, Sungwon Cho, Yu-gwang Jeong, Sanggab Kim
  • Patent number: 11211441
    Abstract: An OLED device includes a substrate, a first active layer, a first gate electrode, a second gate electrode, first source and first drain electrodes, a first high dielectric constant (high-k) insulation structure, and a light emitting structure. The substrate has a first region and a second region. The first active layer is disposed in the first region on the substrate. The first gate electrode is disposed on the first active layer, and has a first thickness. The second gate electrode is disposed on the first gate electrode. The first source electrode and first drain electrode are disposed on the second gate electrode, and constitutes a first semiconductor element together with the first active layer and the first gate electrode. The first high-k insulation structure is disposed between the first gate electrode and the second gate electrode, and is spaced apart from the first source electrode and first drain electrode.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 28, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yu-Gwang Jeong, Subin Bae, Joongeol Lee, Sanggab Kim
  • Publication number: 20210384287
    Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Sang Gab KIM, Hyun Min CHO, Tae Sung KIM, Yu-Gwang JEONG, Su Bin BAE, Jin Seock KIM, Sang Gyun KIM, Hyo Min KO, Kil Won CHO, Hansol LEE
  • Patent number: 11183518
    Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yu-Gwang Jeong, Hyun Min Cho, Su Bin Bae, Shin Il Choi, Sang Gab Kim
  • Patent number: 11127724
    Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 21, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Bin Bae, Yu Gwang Jeong, Shin Il Choi, Joon Geol Lee, Sang Gab Kim