Patents by Inventor Yu-Han Tsai
Yu-Han Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240251509Abstract: A method for manufacturing an electronic device is disclosed. The electronic device has a first region and a transparent region. The method includes the steps of providing a flexible substrate, forming an electric circuit layer on the flexible substrate at an elevated temperature, forming an opening in the transparent region after forming the electric circuit layer, wherein the opening penetrates through a portion of the electric circuit layer, and forming a filling layer on the flexible substrate after forming the opening, wherein at least a part of the filling layer is formed in the opening to enhance a transmittance of the transparent region.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Applicant: InnoLux CorporationInventors: Yu-Chia HUANG, Kuan-Feng Lee, Tsung-Han Tsai
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Publication number: 20240239269Abstract: A vehicle optical system in a vehicle is provided. The vehicle optical system is configured to emit an image to a windshield of a vehicle. The vehicle optical system includes a processor, a display device, and a sensor. The display device electrically connects to the processor. The display device includes a display panel and a plurality of light emitting units. The light emitting units are configured to emit a first light to the display panel. The display panel is configured to output a second light having the image. The sensor electrically connects to the processor, and detects an intensity of ambient light. The processor is configured to modulate the display device to adjust the second light based on the intensity of the ambient light.Type: ApplicationFiled: March 28, 2024Publication date: July 18, 2024Applicant: Innolux CorporationInventors: Yu-Chia Huang, Tsung-Han Tsai, Kuan-Feng Lee
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Patent number: 11912006Abstract: A continuous manufacturing equipment of an elastic three-dimensional fabric and a continuous manufacturing method thereof are disclosed. The continuous manufacturing equipment includes: a film conveying device having a thermal melting film and a conveying mechanism; a cutting device used for cutting a plurality of cutting gaps on the thermal melting film; a first fabric laminating device adhering an outer fabric on one surface of the thermal melting film; and a second fabric laminating device adhering an elastic fabric on another surface of the thermal melting film in a manner of elastically stretching and then elastically recovering. As such, effects of automatic, continuous, and simple steps in manufacturing and having a high yield rate are provided.Type: GrantFiled: May 10, 2022Date of Patent: February 27, 2024Assignee: TAIWAN TEXTILE FEDERATION, R.O.C.Inventors: Shu-Hui Huang, Hung-Kung Chien, Yu-Han Tsai
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Publication number: 20230364897Abstract: A continuous manufacturing equipment of an elastic three-dimensional fabric and a continuous manufacturing method thereof are disclosed. The continuous manufacturing equipment includes: a film conveying device having a thermal melting film and a conveying mechanism; a cutting device used for cutting a plurality of cutting gaps on the thermal melting film; a first fabric laminating device adhering an outer fabric on one surface of the thermal melting film; and a second fabric laminating device adhering an elastic fabric on another surface of the thermal melting film in a manner of elastically stretching and then elastically recovering. As such, effects of automatic, continuous, and simple steps in manufacturing and having a high yield rate are provided.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Inventors: Shu-Hui HUANG, Hung-Kung CHIEN, Yu-Han TSAI
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Publication number: 20230215801Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.Type: ApplicationFiled: February 14, 2022Publication date: July 6, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
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Patent number: 11646264Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.Type: GrantFiled: February 4, 2021Date of Patent: May 9, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
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Publication number: 20220216144Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.Type: ApplicationFiled: February 4, 2021Publication date: July 7, 2022Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
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Patent number: 11127675Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.Type: GrantFiled: December 11, 2019Date of Patent: September 21, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
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Publication number: 20210159170Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.Type: ApplicationFiled: December 11, 2019Publication date: May 27, 2021Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
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Patent number: 10600732Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.Type: GrantFiled: September 5, 2018Date of Patent: March 24, 2020Assignee: United Microelectronics Corp.Inventors: Min-Shiang Hsu, Yu-Han Tsai, Yi-Hsiu Chen, Chih-Sheng Chang
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Publication number: 20200075480Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Applicant: United Microelectronics Corp.Inventors: Min-Shiang Hsu, Yu-Han Tsai, Yi-Hsiu Chen, Chih-Sheng Chang
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Patent number: 10520995Abstract: A portable electronic module includes a casing having an air inlet, a heat generating member disposed in the casing, and a heat dissipating mechanism. The heat dissipating mechanism includes a fixing frame disposed at the casing corresponding to the air inlet, a driving handle, a driving device for driving the driving handle to move reciprocally, and a plurality of fans. The driving handle is disposed at a side of the fixing frame and has a plurality of holes arranged alternately. The fans are pivotally connected to the fixing frame in an alternate arrangement so as to swing relative to the fixing frame. Each fan has a protruding pillar extending toward the corresponding hole. Each protruding pillar is movably disposed through the corresponding hole, so that each fan could swing with reciprocation of the driving handle to guide airflow to pass through the air inlet to the heat generating member.Type: GrantFiled: September 17, 2013Date of Patent: December 31, 2019Assignee: Wistron CorporationInventors: Kai-Yu Chu, Shao-Huai Tsai, Yu-Han Tsai, Yi-Hsieh Chiou
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Patent number: 9312208Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.Type: GrantFiled: October 22, 2014Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
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Patent number: 9042104Abstract: A portable electronic device includes an electronic module and an electronic module fixing structure. The electronic module fixing structure includes a main body, a sliding component, a rod and an elastic component connected between the main body and the sliding component. The main body has a track with a positioning portion. The sliding component is slidably disposed on the main body. The rod is rotatably connected with the sliding component. An end of the rod is adapted to move along the track. When the end is located at the positioning portion, the end and the positioning portion are interfered with each other to position the sliding component. When the electronic module pushes the sliding component, the rod is rotated to drive the end to move away from the positioning portion, and the sliding component pushes the electronic module away from the main body through elastic force of the elastic component.Type: GrantFiled: August 28, 2012Date of Patent: May 26, 2015Assignee: Wistron CorporationInventors: Yu-Han Tsai, Chun-Wang Lin, Ching-Wei Ku, Chia-Hsing Yu, Yao-Te Tsai, Chia-Hung Tsai
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Publication number: 20150041961Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.Type: ApplicationFiled: October 22, 2014Publication date: February 12, 2015Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
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Patent number: 8943649Abstract: A hinge includes a pivot, two connection members pivotally connected by the pivot, a first magnetic part connected to one of the connection members, a second magnetic part moveably disposed relative to the first magnetic part and kinetically connected to the other one of the connection members, and an adjustment part kinetically connected to the other connection member and urging against the adjustment part. The magnetic moment of the second magnetic part is opposite to that of the first magnetic part. When the two connection members rotate relatively, the other connection member drives the adjustment part and the second magnetic part to rotate relative to the first magnetic part, so as to produce a repulsive moment resisting the rotation and varies with the rotation. A foldable electronic apparatus has the hinge.Type: GrantFiled: July 24, 2013Date of Patent: February 3, 2015Assignee: Wistron CorporationInventors: Yuan-Tai Chen, Shao-Huai Tsai, Kai-Yu Chu, Yu-Han Tsai
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Publication number: 20150011149Abstract: A portable electronic module includes a casing having an air inlet, a heat generating member disposed in the casing, and a heat dissipating mechanism. The heat dissipating mechanism includes a fixing frame disposed at the casing corresponding to the air inlet, a driving handle, a driving device for driving the driving handle to move reciprocally, and a plurality of fans. The driving handle is disposed at a side of the fixing frame and has a plurality of holes arranged alternately. The fans are pivotally connected to the fixing frame in an alternate arrangement so as to swing relative to the fixing frame. Each fan has a protruding pillar extending toward the corresponding hole. Each protruding pillar is movably disposed through the corresponding hole, so that each fan could swing with reciprocation of the driving handle to guide airflow to pass through the air inlet to the heat generating member.Type: ApplicationFiled: September 17, 2013Publication date: January 8, 2015Applicant: Wistron CorporationInventors: Kai-Yu Chu, Shao-Huai Tsai, Yu-Han Tsai, Yi-Hsieh Chiou
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Publication number: 20140376180Abstract: A hinge includes a pivot, two connection members pivotally connected by the pivot, a first magnetic part connected to one of the connection members, a second magnetic part moveably disposed relative to the first magnetic part and kinetically connected to the other one of the connection members, and an adjustment part kinetically connected to the other connection member and urging against the adjustment part. The magnetic moment of the second magnetic part is opposite to that of the first magnetic part. When the two connection members rotate relatively, the other connection member drives the adjustment part and the second magnetic part to rotate relative to the first magnetic part, so as to produce a repulsive moment resisting the rotation and varies with the rotation. A foldable electronic apparatus has the hinge.Type: ApplicationFiled: July 24, 2013Publication date: December 25, 2014Applicant: Wistron CorporationInventors: Yuan-Tai Chen, Shao-Huai Tsai, Kai-Yu Chu, Yu-Han Tsai
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Patent number: 8916471Abstract: A method for forming a through silicon via for signal and a shielding structure is provided. A substrate is provided and a region is defined on the substrate. A radio frequency (RF) circuit is formed in the region on the substrate. A through silicon trench (TST) and a through silicon via (TSV) are formed simultaneously, wherein the TST encompasses the region to serve as a shielding structure for the RF circuit. A metal interconnection system is formed on the substrate, wherein the metal interconnection system comprises a connection unit that electrically connects the TSV to the RF circuit to provide a voltage signal.Type: GrantFiled: August 26, 2013Date of Patent: December 23, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Li Yang, Chien-Li Kuo, Chung-Sung Chiang, Yu-Han Tsai, Chun-Wei Kang
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Publication number: 20140368034Abstract: A power supply system used in an electronic device includes a light absorption device, exposed to a backlight source of the electronic device, for absorbing backlight irradiated by the backlight source; an energy conversion circuit, coupled to the light absorption device, for converting the backlight irradiated by the backlight source into electrical power; and a power storage device, coupled to the energy conversion circuit, for storing the electrical power of the energy conversion circuit.Type: ApplicationFiled: September 24, 2013Publication date: December 18, 2014Applicant: Wistron CorporationInventors: Yuan-Tai Chen, Kai-Hou Lin, Shao-Huai Tsai, Kai-Yu Chu, Yu-Han Tsai