Patents by Inventor Yu-Han Tsai

Yu-Han Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111078
    Abstract: A method forming a grating device includes: providing a substrate; entering the substrate into a process chamber; and depositing a grating material on the substrate to form a grating material layer on the substrate. A refractive index of the grating material gradually changes during depositing the grating material in the process chamber. The grating material layer includes a varying refractive index.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Chun-Wei HUANG, Yu-Shan TSAI, Po-Han FU
  • Patent number: 11942007
    Abstract: A transparent display device is provided. The transparent display device includes a display unit having a circuit area and a transparent area. The display unit includes a plurality of signal lines located in the circuit area, a plurality of pixel circuits electrically connected to the signal lines and located in the circuit area, a plurality of light-emitting elements driven by the pixel circuits and located in the circuit area, and an encapsulation layer located in the circuit area and the transparent area. A first thickness of the encapsulation layer located in the circuit area is different from a second thickness of the encapsulation layer located in the transparent area.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 26, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Chia Huang, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20240095755
    Abstract: A hybrid method for green intelligent manufacturing (GiM) combines the carbon reduction and the energy saving into the intelligent manufacturing based Industry 4.1 cloud platform. GiM assists companies to achieve the goal of net zero transition and help them advance to Industry 4.2 as soon as possible by simultaneously taking carbon footprint and energy issues into account. GiM collects large volumes of essential data (including carbon footprint) via cyber physical agents (CPAs), and sends them to two critical services of carbon management and intelligent energy management system (iEMS) deployed on the cloud platform. The two critical services optimize the energy dispatch schedule by strictly following the requirements of energy saving, carbon reduction, and net zero. Then, the state of zero defects of intelligent manufacturing achieved in Industry 4.1 can be upgraded to net zero of GiM in Industry 4.2.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 21, 2024
    Inventors: Hao TIENG, Fan-Tien CHENG, Ting-Chia OU, Tsung-Han TSAI, Yu-Yong LI
  • Publication number: 20240097444
    Abstract: Embodiments of the present invention provide a hybrid system and method for distributed virtual power plants integrated intelligent net zero. In this method, a cyber physical agent (CPA) is utilized to collect a carbon emission information and an energy management information, and then an artificial intelligence (AI) optimization model of an intelligent central dispatch platform is utilized to obtain a power dispatch manner of the distributed virtual power plants based on the carbon emission information and the energy management information, such that the power dispatch manner of the distributed virtual power plants meets the requirements of enterprise economic benefits and net zero carbon emissions at the same time.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 21, 2024
    Inventors: Ting-Chia OU, Hao TIENG, Fan-Tien CHENG, Tsung-Han TSAI, Yu-Yong LI
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11928261
    Abstract: The disclosure provides a display device. The display device includes a display panel and a vibration generating module. The vibration generating module is attached to the display panel and includes a substrate, a circuit layer, and a plurality of vibrators. The circuit layer and the plurality of vibrators are disposed on the substrate, and the plurality of vibrators are electrically connected to the circuit layer.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: March 12, 2024
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Hsiao-Lang Lin, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Patent number: 11912006
    Abstract: A continuous manufacturing equipment of an elastic three-dimensional fabric and a continuous manufacturing method thereof are disclosed. The continuous manufacturing equipment includes: a film conveying device having a thermal melting film and a conveying mechanism; a cutting device used for cutting a plurality of cutting gaps on the thermal melting film; a first fabric laminating device adhering an outer fabric on one surface of the thermal melting film; and a second fabric laminating device adhering an elastic fabric on another surface of the thermal melting film in a manner of elastically stretching and then elastically recovering. As such, effects of automatic, continuous, and simple steps in manufacturing and having a high yield rate are provided.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN TEXTILE FEDERATION, R.O.C.
    Inventors: Shu-Hui Huang, Hung-Kung Chien, Yu-Han Tsai
  • Publication number: 20230364897
    Abstract: A continuous manufacturing equipment of an elastic three-dimensional fabric and a continuous manufacturing method thereof are disclosed. The continuous manufacturing equipment includes: a film conveying device having a thermal melting film and a conveying mechanism; a cutting device used for cutting a plurality of cutting gaps on the thermal melting film; a first fabric laminating device adhering an outer fabric on one surface of the thermal melting film; and a second fabric laminating device adhering an elastic fabric on another surface of the thermal melting film in a manner of elastically stretching and then elastically recovering. As such, effects of automatic, continuous, and simple steps in manufacturing and having a high yield rate are provided.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Shu-Hui HUANG, Hung-Kung CHIEN, Yu-Han TSAI
  • Publication number: 20230215801
    Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.
    Type: Application
    Filed: February 14, 2022
    Publication date: July 6, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Patent number: 11646264
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 9, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Publication number: 20220216144
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.
    Type: Application
    Filed: February 4, 2021
    Publication date: July 7, 2022
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Patent number: 11127675
    Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Publication number: 20210159170
    Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.
    Type: Application
    Filed: December 11, 2019
    Publication date: May 27, 2021
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Patent number: 10600732
    Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Yi-Hsiu Chen, Chih-Sheng Chang
  • Publication number: 20200075480
    Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Yi-Hsiu Chen, Chih-Sheng Chang
  • Patent number: 10520995
    Abstract: A portable electronic module includes a casing having an air inlet, a heat generating member disposed in the casing, and a heat dissipating mechanism. The heat dissipating mechanism includes a fixing frame disposed at the casing corresponding to the air inlet, a driving handle, a driving device for driving the driving handle to move reciprocally, and a plurality of fans. The driving handle is disposed at a side of the fixing frame and has a plurality of holes arranged alternately. The fans are pivotally connected to the fixing frame in an alternate arrangement so as to swing relative to the fixing frame. Each fan has a protruding pillar extending toward the corresponding hole. Each protruding pillar is movably disposed through the corresponding hole, so that each fan could swing with reciprocation of the driving handle to guide airflow to pass through the air inlet to the heat generating member.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 31, 2019
    Assignee: Wistron Corporation
    Inventors: Kai-Yu Chu, Shao-Huai Tsai, Yu-Han Tsai, Yi-Hsieh Chiou
  • Patent number: 9312208
    Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
  • Patent number: 9042104
    Abstract: A portable electronic device includes an electronic module and an electronic module fixing structure. The electronic module fixing structure includes a main body, a sliding component, a rod and an elastic component connected between the main body and the sliding component. The main body has a track with a positioning portion. The sliding component is slidably disposed on the main body. The rod is rotatably connected with the sliding component. An end of the rod is adapted to move along the track. When the end is located at the positioning portion, the end and the positioning portion are interfered with each other to position the sliding component. When the electronic module pushes the sliding component, the rod is rotated to drive the end to move away from the positioning portion, and the sliding component pushes the electronic module away from the main body through elastic force of the elastic component.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: May 26, 2015
    Assignee: Wistron Corporation
    Inventors: Yu-Han Tsai, Chun-Wang Lin, Ching-Wei Ku, Chia-Hsing Yu, Yao-Te Tsai, Chia-Hung Tsai
  • Publication number: 20150041961
    Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang