Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A system for adjusting a control pedal distance and orientation relative to a user of a driving-related assembly, the system comprising a moveable pedal plate having a pedal assembly attachment region and at least one distal attachment point located near a distal end region thereof, and at least one proximal pivotable attachment point, each of the distal attachment point and proximal pivotable attachment point having respective distal coupling means and proximal pivotable coupling means. The system further comprises a connecting member having a pivotable coupling means located near respective first and second ends, wherein the pivotable coupling means located near the first end is matable with the proximal pivotable coupling means, and the second end is matable with a connecting member anchor. The system further comprises at least one substantially upright fixation member having a plurality of predetermined coupling points.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may cool them when their temperatures fall outside of thermal operating ranges. To facilitate cooling, fans may be densely packed and arranged in a manner the occupies a majority of the space in a stack up. At least one side of the fans may be exposed and may not be covered.

Abstract: Methods, systems, and devices for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer-implemented services. To provide the computer-implemented services, hardware components of the data processing system may need to operate within certain thermal dissipation requirements. To regulate the temperature of the hardware components, a fan may circulate air through the data processing system when the temperatures fall outside the thermal dissipation requirements. To regulate the temperature of the hardware components more efficiently, higher air flow rates may be desired. To increase air flow rates, a three-dimensional ventilation port may be implemented to de-constrict air flow when air enters or exits the data processing system.

Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services, a data processing system may include hardware components that provide the computer implemented services. Any of the hardware components may have a limited thermal operating range. To retain the temperatures of hardware components within their operating ranges, the data processing system may include heat sinks fitted to the hardware components that are both able to cool and warm the fitted hardware components.

Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services, the quantity of hardware resources available for providing the computer implemented services may be modified. The quantity of hardware resources may be modified by adding removable cards to a host system. The host system may, while the added removable cards are cold, selectively warm the removable cards through conduction heating to retain their temperatures within operating temperature ranges.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A probe card, a method for designing the probe card, a method for producing a tested semiconductor device, a method for testing an unpackaged semiconductor by the probe card, a device under test, and a probe system are provided. The probe card includes a wiring substrate, a connection carrier board, and a probe device. At least two probes form a differential pair electrically connected to a loopback line of the connection carrier board to form a test signal loopback path. The probe device has a probe device impedance on the test signal loopback path. The loopback line has a loopback line impedance on the test signal loopback path. A difference between the probe device impedance on the test signal loopback path and the loopback line impedance on the test signal loopback path is in an impedance range.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: Silicon Photonics (SiPh) device methods and systems include providing a PDK cell library with parameters for standard SiPh device parameterized cells (Pcells). A custom SiPh layout that includes a plurality of dummy layers defining a custom SiPh device Pcell is created. A schematic including a plurality of the standard SiPh device Pcells and the custom SiPh device Pcell is created, as well as a configuration database correlating the standard SiPh device Pcells and the custom SiPh Pcell to the schematic. The standard SiPh device Pcells and the custom SiPh Pcell are automatically placed and routed based on the configuration database. A plurality of LVS rules are determined based on the dummy layers, and conducting an LVS verification is conducted based on the LVS rules.

Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.

Abstract: A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method further includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and forming a conductive structure over and electrically connected to the thermal control mechanism. The method further includes forming a second dielectric layer over the first dielectric layer and surrounding the conductive structure.

Abstract: A semiconductor device includes an integrated passive device coupled to a redistribution structure by a plurality of first bumps, and having a plurality of second bumps disposed opposite the plurality of first bumps, wherein the plurality of first and second bumps are thermally and/or electrically connected, and thus enable further thermal and/or electrical connections within or comprising the semiconductor device.

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.