Patents by Inventor Yu Hou

Yu Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137110
    Abstract: A method for reducing frequency interference, and a communication satellite system. The method includes configuring the communication satellite system, determining a first range of areas in which a spatial isolation angle between the LEO satellite and the GEO satellite does not satisfy a minimum spatial isolation angle within service areas of the movable spot beams, enabling the movable spot beams to not enter the areas, and when the movable spot beams of the transmitting and receiving user antennas of multiple adjacent LEO satellites provide services to a same area, calculating a spatial isolation angles between the movable spot beams of the transmitting and receiving user antennas of any two adjacent LEO satellites, and in response to the spatial isolation angle not satisfying the minimum spatial isolation angle, assigning different sub-frequencies to the movable spot beams that do not satisfy the minimum spatial isolation angle.
    Type: Application
    Filed: September 29, 2021
    Publication date: April 25, 2024
    Inventors: Fenglong Hou, Feng Li, Xiaoxiong Lin, Yu Qi, Shengwei Pei, Dong Chen, Jie Xing, Hua Huang, Xingang Li, Jincheng Tong, Hengchao Sun, Shaoran Liu, Zeyu Bao
  • Publication number: 20240128232
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Publication number: 20240130139
    Abstract: A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.
    Type: Application
    Filed: July 26, 2023
    Publication date: April 18, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhaozhao Hou, Sitong Bu, Yichen Fang, Yu Zhang, JEFFREY JUNHAO XU
  • Patent number: 11960749
    Abstract: A host of a storage system is coupled to multiple SSDs. Each SSD is configured with a migration cache, and each SSD corresponds to one piece of access information. The host obtains migration data information of to-be-migrated data in a source SSD, determines a target SSD, and sends a read instruction carrying information about to-be-migrated data and the target SSD to the source SSD. The source SSD reads a data block according to the read instruction from a flash memory of the source SSD into a migration cache of the target SSD. After a read instruction is completed by the SSD, the host sends a write instruction to the target SSD to instruct the target SSD to write the data block in the cache of the target SSD to a flash memory of the target SSD.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: April 16, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ge Du, Yu Hu, Jiancen Hou
  • Patent number: 11960356
    Abstract: Methods, systems, and computer-readable storage media for receiving, by an operation guard system executed within a cloud platform, session information representative of a session of a user within the cloud platform, the session information including user information and operation information, determining, by the operation guard system, that the user is signed into a technical group for execution of an operation represented in the operation information, and in response, providing, by the operation guard system, a risk score associated with the operation, and determining, by the operation guard system and at least partially based on the risk score, that the operation is a risk-oriented operation based on the risk score, and in response, preventing execution of the operation and transmitting an alert.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: April 16, 2024
    Assignee: SAP SE
    Inventors: Yu Wang, Le Zhang, Moritz Semler, Daping Wang, Haoxing Hou, Zuosui Wu
  • Patent number: 11963300
    Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 16, 2024
    Assignee: Au Optronics Corporation
    Inventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
  • Patent number: 11954696
    Abstract: A computer system identifies supplemental materials most effective at increasing adherence for each of a plurality of different medications and provides the materials at an optimal point in time. An example method generates a first user interface for receiving an electronic prescription for a patient for a prescribed substance. Responsive to receiving the electronic prescription, the method includes obtaining adherence data for the patient, identifying supplemental programs associated with the prescribed substance from a database of supplemental programs, generating a second user interface that presents the supplemental programs for selection by the health care provider, and responsive to receiving selection of at least one of the supplemental programs in the second user interface, providing the supplemental programs to the patient. The supplemental programs identified from the database are associated with at least one rule relating to adherence data that is met by the adherence data for the patient.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: April 9, 2024
    Assignee: DrFirst.com, Inc.
    Inventors: Kamal Tayal, Andrew Mutch Curtis, Yixin Hou, Christopher John Cresswell, Dennis DiVenuta, Yu-Fui Hung
  • Patent number: 11947500
    Abstract: Various examples are directed to systems and methods for operating a database management system (DBMS) in a cloud environment. An assembly worker executing at a first computing device may provide a first database protocol message generated by a process code executing at the first computing device. A translation engine executed at the cloud environment may translate the first database protocol message from a first format to a second format associated with a DBMS instance executing at the cloud environment to generate a translated first database protocol message. The translation engine may cause the translated first database protocol message to be provided to the DBMS instance and may receive, from the DBMS instance, a first reply corresponding to the translated first database protocol message. The first reply may be sent to the process code.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 2, 2024
    Assignee: SAP SE
    Inventors: Yu Wang, Moritz Semler, Kai Mueller, Le Zhang, Zuosui Wu, Haoxing Hou
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Publication number: 20240099030
    Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.
    Type: Application
    Filed: April 20, 2023
    Publication date: March 21, 2024
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Kuo-Chiang Ting, Chia-Hao Hsu, Hsien-Pin Hsu, Chih-Ta Shen, Shang-Yun Hou
  • Publication number: 20240096719
    Abstract: A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Chien-Yuan Huang
  • Publication number: 20240087955
    Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Inventors: Yi XU, Xianyuan ZHAO, Zhimin QI, Aixi ZHANG, Geraldine VASQUEZ, Dien-Yeh WU, Wei LEI, Xingyao GAO, Shirish PETHE, Wenting HOU, Chao DU, Tsung-Han YANG, Kyoung-Ho BU, Chen-Han LIN, Jallepally RAVI, Yu LEI, Rongjun WANG, Xianmin TANG
  • Publication number: 20240081154
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Publication number: 20240073360
    Abstract: Embodiments of this application relate to the technical field of video shooting, and provide a video processing method and apparatus, an electronic device, and a storage medium. The video processing method includes: determining one video storage resolution; determining one video style template; obtaining a video shot through a camera lens; snapping a corresponding image in the video as a snapped image in response to a snapping instruction; processing the video by using a LOG curve; processing the snapped image by using the LOG curve; converting a LOG video into a determined video storage resolution if the determined video storage resolution is less than a preset resolution, and processing the LOG video based on a LUT; and processing a LOG-based snapped image based on the LUT, where a resolution of the snapped image is equal to the preset resolution.
    Type: Application
    Filed: May 24, 2022
    Publication date: February 29, 2024
    Inventors: Hantao CUI, Weilong HOU, Guoqiao CHEN, Yu Wang
  • Publication number: 20240071888
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
  • Publication number: 20240063255
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.
    Type: Application
    Filed: July 7, 2023
    Publication date: February 22, 2024
    Inventors: SZU-YU HOU, LI-HAN LIN
  • Publication number: 20240063254
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: SZU-YU HOU, LI-HAN LIN
  • Publication number: 20230395388
    Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Li-Han LIN, Jr-Chiuan WANG, Szu-Yu HOU
  • Publication number: 20230395387
    Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: LI-HAN LIN, JR-CHIUAN WANG, SZU-YU HOU
  • Publication number: 20230234973
    Abstract: An intermediate is provided herein, and it has the structure shown in the formula (1) as follows: formula (1). In the formula (1), R1 is —Cl, —Br, —I, —OSO2CF3, —B(OH)2, or R2 is —F, —18F, —Cl, —Br, —I, —SnMe3, —SnBu3, —B(OH)2, or and A is a chiral auxiliary.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 27, 2023
    Applicant: Heron Neutron Medical Corp.
    Inventors: Teng-San Hsieh, Yu-Hou Yu, Tzung-Yi Lin