Patents by Inventor Yu Hou

Yu Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8445363
    Abstract: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 21, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Tsuo-Wen Lu, I-Ming Lai, Tsung-Yu Hou, Chien-Liang Lin, Wen-Yi Teng, Shao-Wei Wang, Yu-Ren Wang, Chin-Cheng Chien
  • Publication number: 20130106711
    Abstract: A hierarchical sensing method for a touch panel is disclosed. The touch panel has a matrix of points for detecting a touch or touches. The method includes dividing the points into a plurality of blocks; selecting several points in each one of the blocks as designated points; sensing first data from each one of the designated points; determining a set of possible touched points according to the first data sensed from each one of the designated points; sensing second data from the set of possible touched points; and determining if each one of the possible touched points is an actual touched point according to the second data sensed from said one possible touched point. By using the present invention method, a faster sensing speed and a greater sensing accuracy can be achieved.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Chen-Yu Hou, Chin-Hua Kuo
  • Publication number: 20130040952
    Abstract: Methods for identifying agents capable of disrupting a salt bridge in an influenza A virus nucleoprotein corresponding to the E339 . . . R416 salt bridge in SEQ ID NO:1, and thus the trimerization of the NP protein; and uses of such agents, e.g., small molecules and peptides, for inhibiting influenza virus replication and treating infection caused by influenza virus.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 14, 2013
    Applicant: Academia Sinica
    Inventors: Chi-Huey Wong, Ming-Daw Tsai, Ying-Ta Wu, Yih-Shyun E. Cheng, Yu-Hou Chen, Yu-Fang Shen
  • Publication number: 20120270382
    Abstract: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Inventors: Tsuo-Wen Lu, I-Ming Lai, Tsung-Yu Hou, Chien-Liang Lin, Wen-Yi Teng, Shao-Wei Wang, Yu-Ren Wang, Chin-Cheng Chien
  • Publication number: 20120245587
    Abstract: A method for spinal drilling operation is disclosed. The method includes the steps of disposing a guiding element on a vertebra; mounting an auxiliary element on a locating part of the guiding element; mounting a k-pin on the auxiliary element; locating the k-pin and removing the auxiliary element from the locating part; mounting a cannular driller having a holding part and a drilling part through the k-pin; and rotating the holding part to drive the drilling part for a reaming process. A guiding assembly for spinal drilling operation is also disclosed. Accordingly, the spinal drilling process can be conducted easier and more precisely.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 27, 2012
    Inventors: Jing-Jing FANG, Ruey-Mo Lin, Izu-Chieh Wu, Cheng-Yu Hou
  • Patent number: 8138515
    Abstract: The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: March 20, 2012
    Assignee: APT Electronics Ltd.
    Inventors: Zhaoming Zeng, Guowei David Xiao, Haiying Chen, Yugang Zhou, Yu Hou
  • Publication number: 20120025241
    Abstract: A surface mounted LED packaging structure based on a silicon substrate includes the silicon substrate, an LED chip, an annular convex wall and a lens. The silicon substrate has an upper surface of planar structure and without grooves. An oxide layer covers the upper surface of the silicon substrate. Metal electrode layers are arranged in the upper surface of the oxide layer, and the upper surfaces of the metal electrode layers are arranged with metal bumps. Vias through the silicon substrate are provided under the metal electrode layers. An insulating layer covers the inner wall of the vias and a part of the lower surface of the silicon substrate. A metal connection layer covers the insulating layer surface within the vias. Two conductive metal pads are respectively arranged under the lower surface of the silicon substrate and insulated from the silicon substrate. A heat conduction metal pad is arranged on the lower surface of the silicon substrate. The LED chip is flip-chip mounted on the silicon substrate.
    Type: Application
    Filed: February 2, 2011
    Publication date: February 2, 2012
    Applicant: APT ELECTRONICS LTD.
    Inventors: Guowei David XIAO, Zhaoming ZENG, Haiying CHEN, Yugang ZHOU, Yu HOU
  • Publication number: 20120025242
    Abstract: The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip.
    Type: Application
    Filed: February 9, 2011
    Publication date: February 2, 2012
    Applicant: APT ELECTRONICS LTD.
    Inventors: Zhaoming ZENG, Guowei David XIAO, Haiying CHEN, Yugang ZHOU, Yu HOU
  • Patent number: 8013709
    Abstract: The present invention provides a conductive module used for assembling a magnetic element and an electronic component. The conductive module includes a conductive base, an electronic component and a plurality of conductive units. The electronic component is electrically connected to the conductive base and disposed on one side of the conductive base. The conductive units have respective hollow portions. The conductive units are spaced from each other and fixed on the conductive base such that the hollow portions of the conductive units are aligned with each other to define a channel.
    Type: Grant
    Filed: February 27, 2010
    Date of Patent: September 6, 2011
    Assignee: Delta Electronics, Inc.
    Inventors: Sheng-Nan Tsai, Yi-Fan Wu, Yung-Sheng Yeh, Jia-Li Tsai, Chia-Cheng Yang, Yung-Yu Chang, Tsung-Sheng Yeh, Hua-Sheng Lin, Chun-Yu Hou, Tsung-Hsiao Wu
  • Publication number: 20110189615
    Abstract: A method of manufacturing MOS transistor includes providing a substrate having a gate formed thereon; forming a hard mask layer on the substrate, performing an acid treatment to a surface of the hard mask layer, forming a photoresist layer on the hard mask layer after performing the acid treatment, performing a photolithography process to pattern the photoresist layer and the hard mask layer, performing an etching process to form recesses in the substrate, and performing a SEG method to form epitaxial layers respectively in the recesses.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 4, 2011
    Inventors: Tsung-Yu Hou, Tai-Heng Yu, Chien-Wei Su, Wen-Yi Teng
  • Publication number: 20100188830
    Abstract: The present invention provides a conductive module used for assembling a magnetic element and an electronic component. The conductive module includes a conductive base, an electronic component and a plurality of conductive units. The electronic component is electrically connected to the conductive base and disposed on one side of the conductive base. The conductive units have respective hollow portions. The conductive units are spaced from each other and fixed on the conductive base such that the hollow portions of the conductive units are aligned with each other to define a channel.
    Type: Application
    Filed: February 27, 2010
    Publication date: July 29, 2010
    Inventors: Sheng-Nan Tsai, Yi-Fan Wu, Yung-Sheng Yeh, Jia-Li Tsai, Chia-Cheng Yang, Yung-Yu Chang, Tsung-Sheng Yeh, Hua-Sheng Lin, Chun-Yu Hou, Tsung-Hsiao Wu
  • Patent number: 7456718
    Abstract: A wire-arranging pin is mounted on a winding frame for facilitating fixing an outlet part of a winding coil. The winding coil is wound around the winding frame. The wire-arranging pin includes a first connecting part, a main fixing part and a second connecting part. The first connecting part has a first end and a second end, wherein the first end is coupled to the winding frame. The main fixing part is coupled to the second end of the first connecting part and has a first notch. The outlet part of the winding coil penetrates through the first notch to be held by the main fixing part. The second connecting part has a first end coupled to the main fixing part.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: November 25, 2008
    Assignee: Delta Electronics, Inc.
    Inventors: Ching-Hsien Teng, Hsin-Wei Tsai, Chun-Yu Hou, Tzu-Yang Liu, Zhi-Liang Zhang, Tsung-Sheng Yeh
  • Patent number: 7157734
    Abstract: Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: January 2, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Haw Tsao, Chender Huang, Shang-Yu Hou, Chao-Yuan Su, Chia-Hsiung Hsu
  • Patent number: 6813642
    Abstract: A communication process by connecting a server end in series with a system under verification (SUV) in a network. The process initializes a communication port connected to server end and SUV and associated parameters through a computer in server end and SUV. Then creates a required thread and an associated interrupt program in server end and SUV respectively. When data has been received, the received data package is stored in an embedded buffer in server end or SUV until a complete data package is stored in the buffer. Next, data is transmitted through a predetermined data transmission module. By continuing this process, it is possible to transmit data by connecting server end in series with SUV through the connected communication port rather than network adapter. It is simple in operation and cost effective.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: November 2, 2004
    Assignee: Inventec Corp.
    Inventors: Kuang-Shin Lin, Tong-S Chen, Zhen-Yu Hou
  • Patent number: 6581169
    Abstract: This specification discloses a method and device for computer testing, which method can perform automatic testing for a plurality of computer on the product line. By describing, recording, and summarizing contents and results of each test item using a script, the defects such as lower efficiency, more errors and longer testing time occurred in human operations can be conquered. The method comprises the steps of: building a structured query language (SQL) server; forming electrical communication between the SQL server and a plurality of computers to be tested; retrieving a command macro from the SQL server according to the-command request sent out from the computer to be tested; controlling the computer to be tested to execute corresponding test commands according to the content of the command macro; receiving and analyzing the execution result of the test command; and displaying the testing result.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: June 17, 2003
    Assignee: Inventec Corporation
    Inventors: Tong S Chen, Kuang Shin Lin, Zhen Yu Hou, Xiao Gang Liou
  • Patent number: 6497489
    Abstract: A projector has a housing, a light source positioned within the housing to generate light, a fan positioned beside the light source to dissipate heat generated by the light source, and an air vent positioned beside the fan to guide heat out of the housing. The air vent reduces turbulence, and thus noise, by the addition of at least one guiding rib. The guiding rib causes heat to flow fluently through the air vent and out of the housing.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: December 24, 2002
    Assignee: Benq Corporation
    Inventors: Chang-Chien Li, Chih-Kang Peng, Yu-Hou Tsao
  • Patent number: D626124
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: October 26, 2010
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yu-Hou Chyan, Teh-Shen Lee
  • Patent number: D640690
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: June 28, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Kuan-Hong Hsieh, Chiang-Kuo Tang, Yu-Hou Chyan
  • Patent number: D642561
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 2, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chiang-Kuo Tang, Yu-Hou Chyan
  • Patent number: D670702
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 13, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chun-Mei Zhang, Chiang-Kuo Tang, Yu-Hou Chyan, Te-Sheng Jan