Patents by Inventor Yu-Hsiang Hung

Yu-Hsiang Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160247678
    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
    Type: Application
    Filed: February 24, 2015
    Publication date: August 25, 2016
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, An-Chi Liu, Chih-Wei Wu, Jyh-Shyang Jenq, Shih-Fang Hong, En-Chiuan Liou, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Mei-Chen Chen, Chia-Hsun Tseng
  • Patent number: 9397190
    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.
    Type: Grant
    Filed: July 27, 2014
    Date of Patent: July 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Man-Ling Lu, Chia-Jong Liu, Wen-Jiun Shen, Yi-Wei Chen
  • Publication number: 20160197162
    Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.
    Type: Application
    Filed: January 28, 2016
    Publication date: July 7, 2016
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20160190287
    Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.
    Type: Application
    Filed: January 28, 2015
    Publication date: June 30, 2016
    Inventors: Chih-Kai Hsu, Chao-Hung Lin, Yu-Hsiang Hung, Ssu-I Fu, Ying-Tsung Chen, Shih-Hung Tsai, Jyh-Shyang Jenq
  • Patent number: 9379119
    Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Yu-Hsiang Hung, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Publication number: 20160163837
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YEN-LIANG WU, CHUNG-FU CHANG, YU-HSIANG HUNG, SSU-I FU, WEN-JIUN SHEN, MAN-LING LU, CHIA-JONG LIU, YI-WEI CHEN
  • Patent number: 9362382
    Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: June 7, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yu-Hsiang Hung, Yen-Liang Wu, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9349833
    Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Chao-Hung Lin, Ying-Tsung Chen, Chih-Kai Hsu, Ssu-I Fu, Jyh-Shyang Jenq, Shih-Hung Tsai
  • Publication number: 20160141386
    Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 19, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YU-HSIANG HUNG, YEN-LIANG WU, SSU-I FU, CHIH-KAI HSU, JYH-SHYANG JENQ
  • Publication number: 20160111448
    Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9318334
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Shih-Hung Tsai, Jyh-Shyang Jenq, Chih-Kai Hsu
  • Patent number: 9318609
    Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
  • Patent number: 9312359
    Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
  • Patent number: 9287263
    Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: March 15, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20160071844
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Application
    Filed: October 13, 2014
    Publication date: March 10, 2016
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Patent number: 9281209
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Ssu-I Fu, Shih-Hung Tsai, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Publication number: 20160064224
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 3, 2016
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Shih-Hung Tsai, Jyh-Shyang Jenq, Chih-Kai Hsu
  • Publication number: 20160064521
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Application
    Filed: November 8, 2015
    Publication date: March 3, 2016
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
  • Publication number: 20160064238
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate.
    Type: Application
    Filed: October 7, 2014
    Publication date: March 3, 2016
    Inventors: Li-Wei Feng, Ssu-I Fu, Shih-Hung Tsai, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Publication number: 20160049467
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Application
    Filed: September 18, 2014
    Publication date: February 18, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YEN-LIANG WU, CHUNG-FU CHANG, YU-HSIANG HUNG, SSU-I FU, WEN-JIUN SHEN, MAN-LING LU, CHIA-JONG LIU, YI-WEI CHEN