Patents by Inventor Yu-Hsiang Hung
Yu-Hsiang Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8993384Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.Type: GrantFiled: June 9, 2013Date of Patent: March 31, 2015Assignee: United Microelectronics Corp.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
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Patent number: 8981487Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.Type: GrantFiled: July 31, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chien-Ting Lin, Po-Chao Tsao, Chung-Fu Chang, Cheng-Guo Chen
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Publication number: 20150035069Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: United Microelectronics Corp.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chien-Ting Lin, Po-Chao Tsao, Chung-Fu Chang, Cheng-Guo Chen
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Publication number: 20140361373Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.Type: ApplicationFiled: June 9, 2013Publication date: December 11, 2014Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
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Publication number: 20140363935Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.Type: ApplicationFiled: June 7, 2013Publication date: December 11, 2014Inventors: Ssu-I Fu, Cheng-Guo Chen, Yu-Hsiang Hung, Chung-Fu Chang, Chien-Ting Lin
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Patent number: 8895396Abstract: An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.Type: GrantFiled: July 11, 2013Date of Patent: November 25, 2014Assignee: United Microelectronics Corp.Inventors: Ssu-I Fu, Yu-Hsiang Hung, Cheng-Guo Chen, Chung-Fu Chang, Chien-Ting Lin
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Publication number: 20140327055Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.Type: ApplicationFiled: May 3, 2013Publication date: November 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
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Publication number: 20140273368Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
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Patent number: 8829575Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.Type: GrantFiled: December 26, 2012Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
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Patent number: 8772120Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.Type: GrantFiled: May 24, 2012Date of Patent: July 8, 2014Assignee: United Microelectronics Corp.Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Shin-Chuan Huang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou
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Publication number: 20140175527Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
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Patent number: 8753902Abstract: A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.Type: GrantFiled: March 13, 2013Date of Patent: June 17, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Jong Liu, Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Pei-Yu Chou, Home-Been Cheng
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Publication number: 20130316506Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Shin-Chuan Huang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou
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Publication number: 20130234261Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: ApplicationFiled: March 12, 2012Publication date: September 12, 2013Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Patent number: 8431460Abstract: A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.Type: GrantFiled: May 27, 2011Date of Patent: April 30, 2013Assignee: United Microelectronics Corp.Inventors: Shin-Chuan Huang, Guang-Yaw Hwang, Hsiang-Ying Wang, Yu-Hsiang Hung, I-Chang Wang
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Publication number: 20130089962Abstract: A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.Type: ApplicationFiled: October 11, 2011Publication date: April 11, 2013Inventors: Chung-Fu Chang, Shin-Chuan Huang, Yu-Hsiang Hung, Chia-Jong Liu, Pei-Yu Chou, Jyh-Shyang Jenq, Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung, Ted Ming-Lang Guo, Chun-Yuan Wu
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Publication number: 20120299058Abstract: A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.Type: ApplicationFiled: May 27, 2011Publication date: November 29, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chuan Huang, Guang-Yaw Hwang, Hsiang-Ying Wang, Yu-Hsiang Hung, I-Chang Wang
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Publication number: 20120037478Abstract: A convey system includes at least three rotatable shafts disposed in substantial parallel with one another. A pair of first rollers are disposed at each of the at least three rotatable shafts. A first distance between the pair of first rollers is fixed at each of the at least three rotatable shafts. At least a pair of second rollers are disposed between the pair of first rollers at each of the at least three rotatable shafts. A second distance between the pair of second rollers is varied at each of the at least three rotatable shafts. The second distance between the pair of second rollers is shortest at a middle one or two of the at least three rotatable shafts and increased gradually from thereof to two opposite ends of the at least three rotatable shafts. In order to prevent the substrate from sliding on the first and second rollers, a sandblasted treating or a roughness coating is applied on an outer surface of the first and second rollers.Type: ApplicationFiled: July 15, 2011Publication date: February 16, 2012Applicant: Du Pont Apollo LimitedInventors: Tai-Hung SHIH, Yu-Hsiang HUNG, Jung-Chin HSU
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Patent number: 7371668Abstract: A method for making a MOS device includes: forming an insulator layer on a semiconductor substrate, the insulator layer including a titanium dioxide film that has a surface with hydroxyl groups formed thereon; and forming an aluminum cap film on the surface of the titanium dioxide film, and conducting annealing operation of the aluminum cap film at an annealing temperature sufficient to permit formation of active hydrogen atoms through reaction of the aluminum cap film and the hydroxyl groups, thereby enabling hydrogen passivation of oxide traps in the titanium dioxide film through diffusion of the active hydrogen atoms into the titanium dioxide film.Type: GrantFiled: November 10, 2005Date of Patent: May 13, 2008Assignee: National Sun Yat-Sen UniversityInventors: Ming-Kwei Lee, Jung-Jie Huang, Yu-Hsiang Hung
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Publication number: 20070105374Abstract: A method for making a MOS device includes: forming an insulator layer on a semiconductor substrate, the insulator layer including a titanium dioxide film that has a surface with hydroxyl groups formed thereon; and forming an aluminum cap film on the surface of the titanium dioxide film, and conducting annealing operation of the aluminum cap film at an annealing temperature sufficient to permit formation of active hydrogen atoms through reaction of the aluminum cap film and the hydroxyl groups, thereby enabling hydrogen passivation of oxide traps in the titanium dioxide film through diffusion of the active hydrogen atoms into the titanium dioxide film.Type: ApplicationFiled: November 10, 2005Publication date: May 10, 2007Inventors: Ming-Kwei Lee, Jung-Jie Huang, Yu-Hsiang Hung