Abstract: An organic semiconductor mixture and an organic optoelectronic device containing the same are provided. A n-type organic semiconductor compound in the organic semiconductor mixture has a novel chemical structure so that the mixture has good thermal stability and property difference during batch production is also minimized. The organic semiconductor mixture is applied to organic optoelectronic devices such as organic photovoltaic devices for providing good energy conversion efficiency while in use.

Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.

Abstract: An organic semiconducting compound and an organic photoelectric component containing the same are provided. The organic semiconducting compound has a novel chemical structure to make the organic semiconducting compound have good response to the infrared light. The organic semiconducting compound can be applied to the organic photoelectric components such as organic photodetector (OPD), organic photovoltaic (OPV) cell, and organic field-effect transistor (OFET). Thus, the organic photoelectric components have better light absorption range and photoelectric response while in use.

Abstract: An electrical connector assembly includes: a bracket; and at least one transmission assembly mounted to the bracket and including an internal printed circuit board (PCB), a board-mount connector connected to a first row of conductive pads disposed at a bottom end portion of the PCB, and a plug-in connector connected to a second row of conductive pads disposed at a front end portion of the PCB, wherein the PCB has a third row of conductive pads disposed at a rear end portion thereof.

Abstract: A memory management method for a storage device having a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of physical blocks. The method includes: scanning the plurality of physical blocks to identify one or more bad physical blocks; performing a bad physical block remapping operation on the one or more bad physical blocks to update a virtual block stripe management table; and performing a writing operation under a multiple plane write mode based on the virtual block stripe management table.

Abstract: A decoding method is provided, and the method includes performing a decoding operation on a plurality of data bit value sets of a codeword. The decoding operation includes following steps: (1) obtaining a syndrome of the data bit value sets; (2) determining whether the codeword is correct or incorrect according to the latest obtained syndrome, wherein if the codeword is correct, the decoding operation is ended, wherein if the codeword is wrong, continuing to step (3) to start an iterative operation; (3) obtaining a plurality of error value sets respectively corresponding to the data bit value sets, wherein in response to obtaining a first error value set, steps (4) and (5) are performed simultaneously; (4) performing an extreme value search operation; (5) performing a bit-flipping operation; and (6) performing a syndrome calculation operation after the step (5) is completed, and performing step (2).

Abstract: A memory management method and a storage controller are provided. The method includes performing a decoding operation to a first data stored in a first word line among multiple word lines of a rewritable non-volatile memory module to determine whether the decoding operation is successful or failed, and obtain a first error value of the first word line; when the decoding operation is determined as successful, determining whether to mark the first word line as a bad word line according to the first error value and a first threshold; and when the decoding operation is determined as failed, obtaining a second error value of a second word line adjacent to the first word line, and determining whether to mark both of the first and second word lines as the bad word line according to the first error value, the second error value, and a first threshold.

Abstract: A data reading method is provided. The method includes: using a predetermined read voltage corresponding to a read operation to read a target physical page to obtain a read codeword syndrome of a read codeword; using a first adjust read voltage to read again the target physical page to obtain a first adjust codeword syndrome of a first adjust codeword; generating soft information of each of a plurality of target memory cells of the target physical page according to the read codeword and the first adjust cordword; identifying a target confidence table according to a size relative relation between the foregoing syndromes to find a confidence value of each of the target memory cells from the target confidence table; and performing an adjusted preset decoding operation according to the soft information and the confidence values to obtain a valid codeword, so as to complete the read operation.

Abstract: A data reading method is provided. The method includes using X read voltage sets to read a target word line, so as to obtain X read results; in a first order, updating a final Gray code index of each of a plurality of target memory cells of the target word line, and obtaining (X?1) abnormal Gray code count sets according to the X read results, wherein an ith read result among the X read results includes a Gray code corresponding to an ith read voltage set of each of the target memory cells, and the Gray code corresponds to one of N Gray code indexes; and selecting (N?1) optimized read voltages from (X?1)*(N?1) read voltages of the corresponding (X?1) read voltage sets to form an optimized read voltage set according to the obtained (X?1) abnormal Gray code count sets.

Abstract: A data writing method is provided. The method includes receiving a first write command and first data corresponding to the first write command from a host system, wherein the first write command instructs to store the first data into a first logical address; copying the first data into a register, responding to the host system that the first write command is completed, and starting to execute a first program operation to program the first data into a first physical page; and in response to determining that the first program operation is failed, reading the first data from the register according to a logical to physical addresses mapping table and mandatorily programming the first data into a second physical page.

Abstract: A data reading method is provided. The method includes: using a predetermined read voltage corresponding to a read operation to read a target physical page to obtain a read codeword syndrome of a read codeword; using a first adjust read voltage to read again the target physical page to obtain a first adjust codeword syndrome of a first adjust codeword; generating soft information of each of a plurality of target memory cells of the target physical page according to the read codeword and the first adjust cordword; identifying a target confidence table according to a size relative relation between the foregoing syndromes to find a confidence value of each of the target memory cells from the target confidence table; and performing an adjusted preset decoding operation according to the soft information and the confidence values to obtain a valid codeword, so as to complete the read operation.

Abstract: A Memory management method for a storage device having a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of physical blocks divided into a plurality of block stripes. The method includes: scanning the physical blocks to identify one or more bad physical blocks among the physical blocks; calculating a plurality of effective weight values corresponding to the block stripes according to a plurality of data accessing time parameters of the rewritable non-volatile memory module, a plurality of valid data counts, and the identified one or more bad physical blocks; and selecting a target block stripe from the block stripes according to the effective weight values to perform a garbage collection operation.

Abstract: A memory management method and a storage controller using the same are provided. The method includes reading a target word-line to identify a plurality of raw Gray code indexes corresponding to a plurality of memory cells of the target word-line; performing a decoding operation on raw data of the target word-line to identify a plurality of decoded Gray code indexes corresponding to the memory cells; calculating a plurality of Gray code absolute bias values corresponding to the memory cells according to the raw Gray code indexes and the decoded Gray code indexes; and identifying one or more abnormal memory cells among the memory cells according to the Gray code absolute bias values; and recording the one or more abnormal memory cells into an abnormal memory cell table, wherein a Gray code absolute bias value of each of the one or more abnormal memory cells is greater than a bias threshold.

Abstract: A memory management method is provided. The method includes: performing a read operation on a target word line; reading a plurality of target physical pages of the target word line to obtain a plurality of hard bit codewords respectively corresponding to the target physical pages; generating soft information of each of a plurality of target memory cells of the target word line according to the hard bit codewords; identifying a plurality of confidence values corresponding to the target physical pages of each of the target memory cells according to a plurality of confidence tables and the soft information of the target memory cells; and performing an adjusted preset decoding operation according to the confidence values and the soft information, so as to obtain a plurality of final decoded codewords respectively corresponding to the target physical pages and complete the read operation.

Abstract: A memory management method is provided. The method includes: performing a read operation on a target word line; reading a plurality of target physical pages of the target word line to obtain a plurality of hard bit codewords respectively corresponding to the target physical pages; generating soft information of each of a plurality of target memory cells of the target word line according to the hard bit codewords; identifying a plurality of confidence values corresponding to the target physical pages of each of the target memory cells according to a plurality of confidence tables and the soft information of the target memory cells; and performing an adjusted preset decoding operation according to the confidence values and the soft information, so as to obtain a plurality of final decoded codewords respectively corresponding to the target physical pages and complete the read operation.

Abstract: A data reading method is provided. The method includes: selecting a target physical page of a target wordline of a rewritable non-volatile memory module; identifying a plurality of distinguishing code patterns corresponding to the target physical page and corresponding one or more transition read voltages; using the one or more transition read voltages to read the target physical page to obtain a distinguishing code of each of a plurality of target memory cells of the target physical page; using one or more assisting read voltage sets corresponding to the one or more transition read voltages to read the target page to obtain an assisting bit value of each of the target memory cells of the target physical page; and combining the distinguishing code and the assisting bit value of each of the target memory cells to obtain an enhanced read bit value of each of the target memory cells.

Abstract: A memory management method is provided. The method includes performing a read voltage optimization operation corresponding to a target physical page among a plurality of physical pages on a target word line to obtain an optimized read voltage set and using the optimized read voltage set to read the target word line after the read voltage optimization operation is completed. The read voltage optimization operation includes: identifying P test codes corresponding to the target physical page and Q transition read voltages corresponding to the P test codes; using the Q transition read voltages and corresponding Q test read voltage sets to read the target word line to obtain Q test code count difference sets; and obtaining the optimized read voltage set according to the Q test code count difference set.

Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes receiving a reading command from a host system; identifying a target physical unit of the rewritable non-volatile memory module according to the reading command, and identifying a program erase cycle value, a first timestamp, a second timestamp of the target physical unit, wherein the first timestamp records a time at which the target physical unit is programmed last, and the second timestamp records a time at which the target physical unit is read last; and selecting a target reading voltage set among a plurality of reading voltage set according to the program erase cycle value, the first timestamp, the second timestamp, so as to read a target data from the target physical unit.

Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.