Patents by Inventor Yu Huang

Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240296268
    Abstract: A method includes tagging source PDK devices (SPDs) in a source-circuit design (SCD); generating a source design simulation database (SDSD) based on source design key performance indicator (KPI) simulation data of the SPDs in the SCD; generating a target process design kit (PDK) simulation database (TPSD) based on target design KPI simulation data of a plurality of target-PDK devices (TPDs); creating a matching table based on the SDSD and the TPSD; matching, based on the matching table, one or more TPDs from the TPSD with each SPD in the SDSD based on SPD KPIs; ranking the one or more TPDs matched from the TPSD with each SPD in the SDSD based on the SPD KPIs; and exchanging, based on a migration mapping table that includes a one-to-one relationship for TPDs to the SPDs in the SCD, one or more SPDs in the SCD with one-to-one relational TPDs.
    Type: Application
    Filed: June 19, 2023
    Publication date: September 5, 2024
    Inventors: Fong-Yuan CHANG, Hui Yu LEE, Yu-Hao CHEN, Tian-Jian WU, Tien-Chien HUANG, Manjo Kumar ENUGULA, Yu-Lin WEI, Jyun-Hao CHANG
  • Publication number: 20240297688
    Abstract: Methods, systems, and devices for wireless communications are described. Generally, the described techniques provide for activating antenna groups at a user equipment (UE) for communications with a base station. The UE may receive an indication of at least one active antenna group for communications with the base station, and the UE may map one or more layers of an uplink message to the at least one active antenna group. The UE may then transmit the one or more layers of the uplink message using the at least one active antenna group based on the mapping. In some cases, the UE may transmit a capability report to the base station indicating one or more antennas in each antenna group in a set of antenna groups at the UE, and the base station may activate the at least one active antenna group from the set of antenna groups.
    Type: Application
    Filed: August 11, 2021
    Publication date: September 5, 2024
    Inventors: Yi HUANG, Hyojin LEE, Yu ZHANG
  • Publication number: 20240298403
    Abstract: The present disclosure provides a circuit board, a chip on film, a display apparatus and a bonding method. The circuit board has a plurality of bonding regions for bonding with a chip on film, each bonding region includes: a plurality of first pins extending along a first direction and sequentially arranged along a second direction; and at least one first alignment mark group on an arrangement path along which the plurality of first pins are arranged and configured to be aligned with a second alignment mark group of the chip on film in a buckled way, so that the plurality of first pins are bonded and attached to second pins of the chip on film in one-to-one correspondence.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 5, 2024
    Inventors: Yunyun LIANG, Changcheng LIU, Jiantao LIU, Liugang ZHOU, Jianwei SUN, Liu HE, Jun WANG, Qing LI, Yu QUAN, Yanting HUANG, Yunlu CHEN, Zhengru PAN
  • Publication number: 20240297166
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: May 15, 2024
    Publication date: September 5, 2024
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240297715
    Abstract: Embodiments of present invention provide a linear-drive pluggable optics (LPO) transceiver. The LPO transceiver includes a receiver path, which includes a receiver optical subassembly (ROSA) converting an input optical signal into an ingress electrical signal; and a linear transimpedance amplifier (TIA) with adjustable frequency transfer function (AFTF), the ingress electrical signal passing through the linear TIA to a host. The LPO transceiver also includes a transmitter path, which includes a linear driver with AFTF receiving an egress electrical signal from the host; and a transmitter optical subassembly (TOSA) converting the egress electrical signal from the linear driver to an output optical signal. A method of operating the LPO transceiver is also included.
    Type: Application
    Filed: July 7, 2023
    Publication date: September 5, 2024
    Inventors: Tongqing Wang, Ming Ding, Xiaolei Huang, Yu Tan, Pengfei He
  • Publication number: 20240296272
    Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Inventors: Pin-Dai SUE, Po-Hsiang HUANG, Fong-Yuan CHANG, Chi-Yu LU, Sheng-Hsiung CHEN, Chin-Chou LIU, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Yi-Kan CHENG
  • Publication number: 20240295837
    Abstract: A developing cartridge includes a casing configured to accommodate developer and having a first side and a second side oppositely arranged in a first direction, and a third side and a fourth side oppositely arranged in the second direction, the first direction and the second direction being intersected with each other. The developing cartridge further includes a developing roller, positioned at the third side, for rotating around a first axis extending in the first direction; a coupling, positioned at the first side, for receiving driving-force output from an image forming device to rotate; a driving surface, inclined to the first direction, including a first driving surface and a second driving surface; a detected part, at least partially positioned at the second side, for moving according to rotation of the coupling.
    Type: Application
    Filed: May 12, 2024
    Publication date: September 5, 2024
    Inventors: Xinyu WU, Yuan LIU, Qin LUO, Hao YANG, Chen CHENG, Wenjie ZHAO, Junyu TAO, Yu CHEN, Baosheng ZHONG, Mingdong CHEN, Yinghao LI, Likun ZENG, Yongdi CHEN, Luofa SU, Haoli HUANG
  • Publication number: 20240294486
    Abstract: Provided are griseofulvin 4 position etherified derivatives and their application thereof. The chemical structures of the griseofulvin 4 position etherified derivatives are drawn in a formula I below. The application of these derivatives includes using the griseofulvin 4 position etherified derivatives as preventive or direct antifungal agents against phytopathogenic fungi.
    Type: Application
    Filed: January 16, 2024
    Publication date: September 5, 2024
    Inventors: Yubin Bai, Meng Zhang, Liangzhu Huang, Yu Zhao
  • Patent number: 12078607
    Abstract: A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Yu Chang, Ken-Ichi Goto, Yen-Chieh Huang, Min-Kun Dai, Han-Ting Tsai, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12079974
    Abstract: An image processing method, where a target area and a background area are determined in an image by performing mask segmentation on the image. Different color processing modes are applied to the target area and the background area, such that luminance of the target area is greater than luminance of the background area, or chrominance of the target area is greater than chrominance of the background area, and a main object corresponding to the target area is more prominently highlighted. This enables a terminal user to have a movie special effect during photographing or video photographing, and improves photographing experience of the user. In addition, the present disclosure further provides a flicker elimination method, such that a color change of video content is smoother and more natural.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 3, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yu Li, Feilong Ma, Tizheng Wang, Xiujie Huang
  • Patent number: 12080646
    Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12080216
    Abstract: A control method of a display panel and a display device are provided. In the method, at least one binding-point grayscale value is obtained at first; an initial-state control parameter, an initial-state brightness parameter, and a reference brightness parameter of a to-be-regulated region are determined according to each of the binding-point grayscale value; and a relative compensation brightness parameter of the binding-point grayscale value is determined according to the initial-state control parameter, the initial-state brightness parameter, and the reference brightness parameter of the binding-point grayscale value when a ratio of the initial-state brightness parameter to the reference brightness parameter is not within a preset range.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: September 3, 2024
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventors: Qiqi Lin, Yu Huang
  • Patent number: 12080769
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, Shih-Chieh Wu, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240286175
    Abstract: A cleaning system and method can include a cleaning device including a soaking tank configured to accommodate cleaner; and a filtering device configured to filter a first substance being a mixture of the cleaner and mask residue in the soaking tank. The filtering device includes a sucking apparatus including an sucking port for sucking the first substance; a spraying apparatus, including a spraying port oriented a region that the sucking port is capable of sucking in a bottom of the soaking tank, the spraying port being configured to spray liquid or gas to flush the bottom of the soaking tank; and a filtering apparatus connected to the sucking apparatus to receive and filter the first substance sucked by the sucking port.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 29, 2024
    Inventors: Yong HUANG, Yu YAO, Yanjie LI
  • Publication number: 20240291529
    Abstract: Methods, systems, and devices for wireless communication are described. In some systems, a base station may transmit subband uplink precoding information to a user equipment (UE). The base station may transmit a first control message to the UE to indicate a set of downlink resources for a downlink message associated with the subband uplink precoding information for the UE. The base station may transmit a second control message to the UE to indicate a set of uplink resources for an uplink message. The base station may transmit the downlink message to the UE via the set of downlink resources indicated by the first control message. The downlink message, the second control message, or both may include the subband uplink precoding information for the UE. The UE may transmit an uplink message to the base station via the set of uplink resources using the subband uplink precoding information.
    Type: Application
    Filed: August 27, 2021
    Publication date: August 29, 2024
    Inventors: Hyojin LEE, Yu ZHANG, Yi HUANG, Wanshi CHEN, Hwan Joon KWON
  • Publication number: 20240291606
    Abstract: Aspects of the disclosure relate to systems and methods for receiving, by a first user equipment (UE), a message comprising at least one of: reference signal information (RS-info) relating to one or more reference signals (RSs) corresponding to line-of-sight (LoS) signals targeting a receiver other than the first UE, and/or data-decoding information relating to data scheduled for purposes of on-going communication with a second UE, and not scheduled for purposes of on-going communication with the first UE. The disclosure also relates to systems and methods for monitoring for at least one of: encoded signals based on the data-decoding information, and/or for one or more RSs based on the RS-info. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: June 11, 2021
    Publication date: August 29, 2024
    Inventors: Qiaoyu Li, Hao Xu, Yu Zhang, Min Huang, Chao Wei, Jing Dai
  • Publication number: 20240289952
    Abstract: The present disclosure is a three-way U-Net method for accurately segmenting an uncertain boundary of a retinal blood vessel, includes: describing an uncertainty of a blood vessel boundary label, constructing an upper bound and a lower bound of the uncertain boundary based on the dilation operator and the erosion operator respectively to obtain a maximum value and a minimum value for the blood vessel boundary, and mapping the boundary with uncertain information into one range; combining an uncertainty representation of the boundary with a loss function, and designing a three-way loss function; training network parameters by adopting a stochastic gradient descent algorithm and utilizing a total loss of the three-way loss function; and designing and implements an auxiliary diagnosis application system for intelligently segmenting the retinal blood vessel with functions of the fundus data acquisition, the intelligent accurate segmentation and the auxiliary diagnosis for the retinal blood vessel.
    Type: Application
    Filed: May 24, 2023
    Publication date: August 29, 2024
    Applicant: NANTONG UNIVERSITY
    Inventors: Weiping DING, Ying SUN, Tao HOU, Xinjie SHEN, Hengrong JU, Jiashuang HUANG, Haipeng WANG, Tingzhen QIN, Yu GENG, Ming LI, Haowen XUE, Zhongyi WANG
  • Publication number: 20240290652
    Abstract: A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.
    Type: Application
    Filed: May 7, 2024
    Publication date: August 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Publication number: 20240286972
    Abstract: Disclosed in the present invention is a thermoplastic composite solid propellant, which comprises, by mass: 5-16% of a thermoplastic elastomer having a bonding function; 5-25% of a plasticizer; 5-18% of a metal fuel; 50-70% of an oxidizing agent; and 0.4-5% of a functional auxiliary agent. In the thermoplastic composite solid propellant, a thermoplastic elastomer grafted or copolymerized with a bonding functional group is used as an adhesive, and an adhesive matrix and a solid filler have relatively strong interaction, such that an interfacial effect is enhanced, and the phenomenon of “dehumidification” in the tensile failure process can be slowed down. Further disclosed is a method for preparing the thermoplastic composite solid propellant. The method overcomes defects in the prior art, safely and efficiently prepares the thermoplastic composite solid propellant in an acoustic resonance mixing manner, and meets the requirements of a solid engine for rapid charging.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 29, 2024
    Applicant: HUBEI INSTITUTE OF AEROSPACE CHEMICAL TECHNOLOGY
    Inventors: Pu Huang, Wei Li, Wei Wang, Yu Shi, Ke Shi, Xiaomeng Fu, Chuntao Li, Fang Wang, Yanwei Wang, Xinke Sun
  • Publication number: 20240290661
    Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang