Patents by Inventor Yu Huang

Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087989
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Publication number: 20240090174
    Abstract: The present disclosure discloses a control device, which comprises: a circuit board; a heat dissipation cover comprising a heat dissipation cover plate and a plurality of heat dissipation fins arranged on the heat dissipation cover plate, wherein the heat dissipation cover plate covers the circuit board, and a groove is formed between the plurality of heat dissipation fins; a thermally conductive strip disposed between the circuit board and the heat dissipation cover plate; and a fan arranged in the groove. The heat dissipation cover disclosed herein covers the circuit board as a holistic upper cover, the heat of the circuit board is conducted to the heat dissipation cover through the thermally conductive strip, and the fan in the through groove generate an airflow to dissipate heat, thereby realizing sealing, dustproof and heat dissipation of the circuit board simultaneously.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Weiwei HUANG, Yu ZHANG, Jianan HAO
  • Publication number: 20240083828
    Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.
    Type: Application
    Filed: June 28, 2023
    Publication date: March 14, 2024
    Inventors: Wen-Hsi HUANG, Sheng-Yen KO, Shih-Hong CHEN, Chun-Yu LIN
  • Publication number: 20240088990
    Abstract: Methods, systems, and devices for wireless communications are described. A first device (e.g., a base station) may transmit reference signals to a second device (e.g., a user equipment (UE)) via transmitter antenna circles. The second device may receive and measure the reference signals via corresponding receiver antenna circles. Both the transmitter antenna circles and the in receiver antenna circles may include a center antenna circle and one or more peripheral antenna circles. The second device may transmit channel gain measurements to the first device based on measuring the reference signals. The first device may determine orbital angular momentum (OAM) modes, a power loading scheme, or both for the transmitter antenna circles based on the channel gain measurements. The first device may transmit OAM transmissions to the second device based on the determined OAM modes, the power loading scheme, or both. The OAM transmissions may have different OAM states, polarizations, or both.
    Type: Application
    Filed: April 2, 2021
    Publication date: March 14, 2024
    Inventors: Danlu ZHANG, Min HUANG, Yu ZHANG, Hao XU
  • Publication number: 20240088119
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240087207
    Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: MediaTek Inc.
    Inventors: Po-Yu HUANG, Shih-Chin LIN, Jen-Jung CHENG, Tu-Hsiu LEE
  • Publication number: 20240087528
    Abstract: A display substrate and a display device are provided. The display substrate includes a first display region including first light emitting unit groups and first pixel circuit groups connected with the first light emitting unit groups, a second display region including second light emitting unit groups, second pixel circuit groups connected with the second light emitting unit groups and third pixel circuit groups, and a third display region including third light emitting unit groups connected with the third pixel circuit groups. Each light emitting unit group includes light emitting units of different colors. The light emitting unit includes a main body electrode, an area of the main body electrode of at least one color light emitting unit in the third display region is greater than that of a main body electrode of the same color light emitting unit in the first display region.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lili DU, Wei ZHANG, Yu ZHANG, Chi YU, Weiyun HUANG
  • Publication number: 20240088980
    Abstract: Certain aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for beam determination, multi-user transmission, and channel state variance information (CSVI) reporting in a holographic multiple input multiple output (MIMO) system.
    Type: Application
    Filed: March 26, 2021
    Publication date: March 14, 2024
    Inventors: Min HUANG, Wei XI, Chao WEI, Yu ZHANG, Hao XU, Chenxi HAO, Rui HU, Liangming WU, Kangqi LIU, Qiaoyu LI, Jing DAI, Changlong XU
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240088195
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20240088071
    Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Yi XU, Yu LEI, Zhimin QI, Aixi ZHANG, Xianyuan ZHAO, Wei LEI, Xingyao GAO, Shirish A. PETHE, Tao HUANG, Xiang CHANG, Patrick Po-Chun LI, Geraldine VASQUEZ, Dien-yeh WU, Rongjun WANG
  • Patent number: 11928289
    Abstract: A touch sensing method for a touch panel includes following operations: entering a first touch sensing process and performing a non-water mode; determining whether there is water on the touch panel in the first touch sensing process; entering a second touch sensing process and performing a water mode when there is water detected on the touch panel in the first touch sensing process; determining whether there is water on the touch panel in the second touch sensing process; and entering the first touch sensing process and performing the non-water mode when there is no water detected on the touch panel in the second touch sensing process.
    Type: Grant
    Filed: July 17, 2022
    Date of Patent: March 12, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yu-Huang Chen, Ting-Yu Chan
  • Patent number: 11928457
    Abstract: Embodiments of the present application provide a server of a battery swapping station, a charging method and system for a battery, a device and a medium. The method is applied to a server of a battery swapping station, and the method includes: acquiring version information of a first software version after a vehicle mounted with a power battery arrives at the battery swapping station, wherein the first software version is a software version of a first battery management unit of the power battery; controlling, under a condition that the version information of the first software version is lower than version information of a second software version stored in the server, a second battery management unit of the battery swapping station to update the first software version of the first battery management unit to the second software version.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: March 12, 2024
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Zhanliang Li, Zhimin Dan, Yu Yan, Miaomiao Zhang, Zhenhui Huang
  • Patent number: 11929319
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20240076396
    Abstract: Provided herein are antibodies, and antigen-binding fragments thereof that specifically bind glucocorticoid-induced tumor necrosis factor receptor (GITR), compositions comprising the antibodies or antigen-binding fragments thereof, and methods of using the same, including, e.g., methods of treatment using the same.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Robert Babb, Drew Dudgeon, Yu Huang, Rosalynn Molden, William Olson, Matthew Sleeman, Dimitris Skokos, Bei Wang
  • Publication number: 20240079358
    Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Siva Sai Kishore Palli, Venkata Rama Satya Pradeep Vempaty, Wen How Sim, Chen Yu Huang, Harjashan Veer Singh
  • Publication number: 20240079278
    Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 7, 2024
    Inventors: Jhih-Yong Han, Wen-Yen Chen, Yi-Ting Wu, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240079277
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, an isolation layer, a gate stack structure, and a dielectric layer. The method includes partially removing the gate stack structure to form a first trench in the gate stack structure. The method includes forming an isolation structure in the first trench. The method includes removing the first gate stack and the second gate stack to form a first recess and a second recess in the dielectric layer. The method includes forming an n-type gate stack and a p-type gate stack in the first recess and the second recess respectively. The method includes forming a conductive line over the n-type gate stack, the p-type gate stack, and the isolation structure. The conductive line electrically connects the n-type gate stack to the p-type gate stack.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wang-Chun HUANG, Pei-Yu WANG
  • Patent number: 11923358
    Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
  • Patent number: 11923366
    Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Kang Ho, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo