Patents by Inventor Yu Huang

Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10855317
    Abstract: An RF receiver includes a low-noise amplifier (LNA) to receive and amplify RF signals, a transformer-based IQ generator circuit, one or more load resisters, one or more mixer circuit, and a downconverter. The transformer-based IQ generator is to generate a differential in-phase local oscillator (LOI) signal and a differential quadrature (LOQ) signal based on a local oscillator (LO) signal received from an LO. The load resisters are coupled to an output of the transformer-based IQ generator. Each of the load resisters is to couple one of the differential LOI and LOQ signals to a predetermined bias voltage. The mixers are coupled to the LNA and the transformer-based IQ generator to receive and mix the RF signals amplified by the LNA with the differential LOI and LOQ signals to generate an in-phase RF (RFI) signal and a quadrature RF (RFQ) signal. The downconverter is to down convert the RFI signal and the RFQ signal into IF signals.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 1, 2020
    Assignee: SWIFTLINK TECHNOLOGIES INC.
    Inventors: Min-Yu Huang, Thomas Chen
  • Patent number: 10854565
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10854297
    Abstract: An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 1, 2020
    Assignee: Yield Microelectronics Corp.
    Inventors: Cheng-Ying Wu, Cheng-Yu Chung, Wen-Chien Huang
  • Patent number: 10853735
    Abstract: Systems, methods, and computer-readable media are disclosed for maximizing quantifiable user interaction via modification of adjustable parameters. In one embodiment, an example method may include determining a first output to maximize, where the first output is a function of a first adjustable parameter and a second adjustable parameter, determining first data comprising a first actual value of the first output when the first adjustable parameter is set to a first value and the second adjustable parameter is set to a second value, and determining a first predictive model that generates a first predicted value of the first output. Example methods may include determining, using the first predictive model, a third value for the first adjustable parameter and a fourth value for the second adjustable parameter to maximize the first predicted value, and sending the third value and the fourth value.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Yu Gan, C├ędric Philippe Archambeau, Rodolphe Jenatton, Jim Huang, Fabian Lutz-Frank Wauthier
  • Patent number: 10854599
    Abstract: A method includes forming a first gate, a second gate, a third gate, and a fourth gate over a substrate, in which a first distance between the first gate and the second gate is less than a second distance between the third gate and the fourth gate. A first spacer over a sidewall of the first gate, a second spacer over a sidewall of the second gate, a third spacer over a sidewall of the third gate, and a fourth spacer over a sidewall of the fourth gate are formed. A mask layer over the first and second spacers is formed, in which the third and fourth spacers are exposed from the mask layer. The exposed third and fourth spacers are trimmed.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
  • Patent number: 10854499
    Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Cheng-I Huang, Hui-Zhong Zhuang, Chi-Yu Lu, Stefan Rusu
  • Patent number: 10854165
    Abstract: A method for calibrating a device having a first sensor and a second sensor. The method includes capturing sensor data using the first sensor and the second sensor. The device maintains a calibration profile including a translation parameter and a rotation parameter to model a spatial relationship between the first sensor and the second sensor. The method also includes determining a calibration level associated with the calibration profile at a first time. The method further includes determining, based on the calibration level, to perform a calibration process. The method further includes performing the calibration process at the first time by generating one or both of a calibrated translation parameter and a calibrated rotation parameter and replacing one or both of the translation parameter and the rotation parameter with one or both of the calibrated translation parameter and the calibrated rotation parameter.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 1, 2020
    Assignee: Magic Leap, Inc.
    Inventors: Yu-Tseh Chi, Jean-Yves Bouguet, Divya Sharma, Lei Huang, Dennis William Strelow, Etienne Gregoire Grossmann, Evan Gregory Levine, Adam Harmat, Ashwin Swaminathan
  • Publication number: 20200374454
    Abstract: A method of automatically recording cosmetology procedure applied to a system of automatically recording cosmetology procedure is to capture detection images continuously, recognize a cosmetic product and start to measure time when determining that a user starts to use the cosmetic product, stop measuring time and record a usage of the cosmetic product in this round when determining that the user stops using the cosmetic product, and output a reminder notification of incorrect procedure when determining that there is incorrect usage of the cosmetic product according to a standard cosmetology procedure. The present disclosed example can record the usage of the cosmetic products automatically, and prevent the user from the incorrect usage of the cosmetic product.
    Type: Application
    Filed: December 9, 2019
    Publication date: November 26, 2020
    Inventors: Ying-Yu CHEN, Yuan-Peng HUANG
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20200373334
    Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee Wee Liu
  • Publication number: 20200374135
    Abstract: A method includes: a supervisor writes a digital certificate and a corresponding first public key into an intelligent contract of a blockchain corresponding to an asset type to be supervised, so that all institutions with asset accounts under the asset type can obtain the first public key of the supervisor through the digital certificate, so as to generate an additive homomorphic key for homomorphic encryption of the balance of an asset account; when checking the balance of a new account of a transactor, the supervisor obtains a public key in a public-private key pair corresponding to the new account, generates an additive homomorphic key based on a supervision private key corresponding to the supervisor and a predetermined key exchange protocol and the public key in the public-private key pair according to the key exchange protocol, and decrypts the encrypted balance of the new account, using the generated additive homomorphic key.
    Type: Application
    Filed: June 30, 2017
    Publication date: November 26, 2020
    Applicant: One Connect Smart Technology Co., Ltd. (Shenzhen)
    Inventors: Frank Yifan Chen Lu, Pengfei Huan, Yu Zhang, Yuxiang Huang
  • Publication number: 20200375040
    Abstract: An electronic device including a housing, a light source, and a printed pattern layer is provided. The housing includes an inner side and an outer side. The light source is disposed on the inner side of the housing. The printed pattern layer covers the outer side of the housing. The printed pattern layer includes a shielding area and a transparent area. A light beam from the light source transmits outward through the transparent area.
    Type: Application
    Filed: October 3, 2019
    Publication date: November 26, 2020
    Inventors: Fu-Yu CAI, Ming-Chih HUANG, Tong-Shen HSIUNG, Meng-Chu HUANG, Shang-Chih LIANG
  • Patent number: 10845526
    Abstract: A pupil replication waveguide for a projector display includes a slab of transparent material for propagating display light in the slab via total internal reflection. A diffraction grating is supported by the slab. The diffraction grating includes a plurality of slanted fringes in a substrate for out-coupling the display light from the slab by diffraction into a blazed diffraction order. A greater portion of the display light is out-coupled into the blazed diffraction order, and a smaller portion of the display light is out-coupled into a non-blazed diffraction order. A refractive index contrast profile of the diffraction grating along a thickness direction of the diffraction grating is symmetrical, and a refractive index contrast is larger at a middle than at both sides of the refractive index contrast profile, whereby the portion of the display light out-coupled into the non-blazed diffraction order is decreased.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 24, 2020
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Hee Yoon Lee, Ningfeng Huang, Pasi Saarikko, Yu Shi, Giuseppe Calafiore, Nihar Ranjan Mohanty
  • Patent number: 10845475
    Abstract: A method of measuring an azimuth of a target by a scanning radar includes (a) establishing a radar scanning model, including (a1) selecting an antenna pattern, (a2) setting a set of radar parameters, (a3) creating reflected signals simulation curve, (a4) sampling the reflected signals simulation curve to create a plurality of sets of simulation data, each set is consisted of successive samples, and (a5) normalizing each sample of each set of simulation data to create a plurality sets of records of normalized simulation data; (b) obtaining normalized scanning data; (c) comparing records of normalized simulation data with the normalized scanning data; and (d) obtaining an azimuth of the target.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 24, 2020
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chun-Jung Lin, Liang-Yu Ou Yang, Po-Yao Huang, Chi-Ming Hsieh
  • Patent number: 10847485
    Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 10847378
    Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
  • Publication number: 20200365563
    Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu CHEN, Li-Hsien HUANG, An-Jhih SU, Hsien-Wei CHEN
  • Publication number: 20200367371
    Abstract: The application discloses an electronic device including a motherboard and a housing structure. The motherboard has a first surface and a second surface. The housing structure includes a first casing, a first cushion, a second casing, and a second cushion. The first casing has at least one first fixing member. The first cushion covers the first surface, is accommodated in the first casing and has at least one first through hole. The second casing has at least one second fixing member. The second cushion covers the second surface, is accommodated in the second casing and has at least one second through hole. A peripheral edge of the first cushion is attached to a peripheral edge of the second cushion, and the first fixing member may be fixed to the second fixing member through the first through hole and the second through hole.
    Type: Application
    Filed: April 6, 2020
    Publication date: November 19, 2020
    Inventors: Kuan-Ting LIN, Wen-Cheng TSAI, Jr-Hung HUANG, Danny SUN, Ho-Ching HUANG, Nien-Yu CHANG, Ming-Ke CHOU
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao