Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Abstract: The present disclosure provides an atomizing device including an outer case and an atomizing component. The outer case has an air inlet. The atomizing component is disposed in the outer case. Wherein, the atomizing component and the outer case jointly form an air outlet, and the air outlet is located on one side of the atomizing component away from the air inlet. Wherein, a diversion channel is formed between the outer case and the atomizing component. The diversion channel surrounds the atomizing component. The air inlet, the diversion channel, and the air outlet are in fluid communication to each other. The gas entering the atomizing device through the diversion channel may have greater kinetic energy, so as to be uniformly mixed with the atomized filler. The evenly mixed smoke may effectively improve the user experience.

Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Abstract: An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

Abstract: A method includes a number of operations. A semiconductor fin is formed and extends from a substrate. A dummy gate structure is formed across the semiconductor fin. An exposed surface of the gate layer is converted into a surface modification layer over the gate layer. Source/drain regions are formed on the semiconductor fin. The dummy gate structure is removed. A gate structure is formed over the semiconductor fin and extends between the source/drain regions and in the surface modification layer.

Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: An image sensor includes a plurality of pixels. At least one pixel includes first and second photosensitive regions, first and second transfer gate transistors and a floating diffusion region. The first and second photosensitive regions are located within a substrate and adjacent to each other. The first and second photosensitive regions are different in at least one of doping depth and conductivity type. The first and second photosensitive regions are overlapped with an opening of a grid structure disposed on a backside surface of the substrate. The first and second transfer gate transistors are disposed on a frontside surface of the substrate and respectively overlapped with the first and second photosensitive regions. The floating diffusion region is located within the substrate and shared between the first and second photosensitive regions.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: The present disclosure provides a semiconductor device, which includes a control circuit, a driving circuit, a voltage pull-up device, and a discharging circuit. The control circuit is coupled between a first terminal and a second terminal of the integrated circuit, and provides a first voltage at a first node. The driving circuit is electrically connected to the control circuit at the first node, and provides a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal. The voltage pull-up device is coupled between the first terminal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal. The discharging circuit is electrically connected to the second node, and coupled between the first terminal and the second terminal.

Abstract: Some implementations herein include a pixel sensor structure and methods of forming. The pixel sensor structure includes a lens structure, a photodiode sensor structure, and an optical spacer structure between the lens structure and the photodiode sensor structure. The lens structure redirects near infrared light through the optical spacer structure and to the photodiode sensor structure to improve the quantum efficiency performance of the photodiode sensor structure relative to another photodiode sensor structure include in a pixel sensor structure without the lens structure and the optical spacer structure. Additionally, different configurations of an anti-reflection coating layer may be included throughout the pixel sensor structure to improve the quantum efficiency performance of the photodiode sensor structure further.

Abstract: A self-centering energy dissipation device is adapted to be connected to first and second objects, and includes a first base seat, at least one main shaft, two second base seats and at least one pair of elastic members. The first base seat is adapted to be connected to the first object. The at least one main shaft extends through the first base seat. The second base seats are connected respectively and movably to two opposite ends of the at least one main shaft and are adapted to be connected to the second object. The at least one pair of elastic members are sleeved on the at least one main shaft. Each of the at least one pair of elastic members has a first end abutting against the first base seat, and a second end abutting against a respective one of the second base seats.

Abstract: The present disclosure discloses an inspection device and an inspection method. The inspection device includes a first light source, a second light source, a light source controller and a sensor. The light source controller is configured to enable the first light source to irradiate an object under inspection in a first period of an inspection phase, and to enable the second light source to irradiate the object under inspection in a second period of the inspection phase. The sensor continuously senses the reflected light of the object under inspection in an exposure period of the inspection phase so as to obtain image data of the object under inspection. The exposure period includes the first period and the second period.

Abstract: A computer system for failing a secure boot in a case tampering event comprises a microcontroller unit (MCU); a trusted platform module (TPM), for generating random bytes for a secure boot of the computer system; a bootloader, for storing information comprising the random bytes in the MCU and at least one hardware of the computer system and performing the secure boot, wherein the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, coupled to the MCU, for detecting a case tampering event, and transmitting a signal for triggering a deletion of the random bytes, if the case tampering event happens. The MCU performs the operation of deleting the random bytes stored in the MCU and the at least one hardware according to a power supply, in response to the signal.

Abstract: A test apparatus has at least one optical source, a high-speed photodetector, a microcontroller or processor, and electrical circuitry to power and drive the optical source, high-speed photodetector, and microcontroller or processor. The apparatus measures the frequency response and optical path length of a multimode optical fiber under test, utilizes a reference VCSEL spatial spectral launch condition and modal-chromatic dispersion interaction data to estimate the channels total modal-chromatic bandwidth of the fiber under test, and computes and presents the estimated maximum data rate the fiber under test can support.

Abstract: The present invention disclose methods for increasing chromium in white kidney bean. The method comprises preparing field, performing a first treatment to the seeds of the white kidney bean, performing a second treatment during the seeding period, performing a third treatment during the flowering period, performing a forth treatment during the fruiting period and performing a fifth treatment during the maturing period. Meanwhile, the amount of chromium in the white kidney bean produced according to the present invention is approximately from 400 to 800 mg/kg.

Abstract: A vending machine for storing and selling restricted commodities, and a vending method implemented therein. In the vending machine, a control module comprises a processor executing program codes to provide a vending service. A user interface is connected to the control module, comprising a sensor sampling biometric characteristics of a user. A communication module is connected to the control module, comprising a wireless transceiver configured to receive commands from the control module, and communicate with a central system or the user. The control module drives said sensor to capture the biometric characteristics of the user, and then uploads the biometric characteristics to the central system through the communications module. A database storing associations of the biometric characteristics and identity characteristics of users. The control module receives a search result from the database based on the biometric characteristics of the user to determine whether a restricted commodity is authorized for sale.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: A summer includes a first transconductance amplifier, a first switch coupled to a first input of the summer, a second switch coupled to a second input of the first transconductance amplifier, and a transimpedance amplifier. A first output of the first transconductance amplifier is coupled to a first input of the transimpedance amplifier, and a second output of the first transconductance amplifier is coupled to a second input of the transimpedance amplifier. The summer also includes a second transconductance amplifier. A tap input of the second transconductance amplifier is configured to receive a first digital code indicating a level decision for a first previous symbol, a first output of the second transconductance amplifier is coupled to the first input of the transimpedance amplifier, and a second output of the second transconductance amplifier is coupled to the second input of the transimpedance amplifier.