Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: A driving mechanism is provided, including a base, a movable unit, a magnetic element, and a driving assembly. The movable unit is movably disposed on the base. The magnetic element is disposed on the movable unit and has plastic material. The driving assembly is configured to drive the movable unit to move relative to the base, wherein the driving assembly has a coil, and the magnetic element and the movable unit move relative to the base when an electrical current is applied to the coil.

Abstract: A display substrate, comprising: a first electrode layer, which is located on one side of a drive backplane and which comprises a plurality of first electrodes that are distributed in an array; a leakage cutoff layer, which is located on the side of the first electrode layer facing away from the drive backplane and is located between two adjacent first electrodes, the surface of the leakage cutoff layer on the side facing away from the drive backplane having a cutoff recess and cutoff protrusions located on both sides of the cutoff recess; a light-emitting functional layer, which is located on the side of the leakage cutoff layer and the first electrode layer facing away from the drive backplane; and a second electrode layer, which is located on the side of the light-emitting functional layer facing away from the drive backplane.

Abstract: An operation method of a heater device with a memory unit, wherein the heater device includes a plurality of heater circuits, each of the plurality of heater circuits includes a first transistor and a second transistor. In a burning mode, selectively turning on at least one of the first transistors according to a first signal, so that a first current generated by voltage signals coupled to two terminals of the first transistor passes through the memory unit. In a reading mode, sequentially turning on the first transistors to determine states of the memory units. In a heating mode, selectively turning on at least one of the second transistors according to a second signal, so that a second current generated by voltage signals coupled to two terminals of the second transistor passes through a heater.

Abstract: An image processing method is provided. The method includes the step of comparing each of the input pixels in an input image to a corresponding buffered pixel in a buffered image, and computing the difference value between the input pixel value of the input pixel and the buffered pixel value of the buffered pixel. The method further includes the step of generating a blended image based on the input pixel values and the corresponding difference values. The method further includes the step of determining whether a criterion associated with the difference value is met, for each of the difference values. The method further includes the step of updating, for each of the buffered pixels in the buffered image, the buffered pixel value based on the corresponding input pixel value if the criterion is met, and keeping the buffered pixel value unchanged if the criterion is not met.

Abstract: An infrared filter film layer and an infrared filter structure are provided. The infrared filter film layer includes at least one silicon-based layer, at least one isolation layer, and at least one oxide layer that are stacked with each other. The at least one isolation layer is disposed between the at least one silicon-based layer and the at least one oxide layer. Through this configuration, the infrared filter film layer has good quality, such that an amount of wavelength drift is small in application. The infrared filter structure includes a light-transmitting substrate and the infrared filter film layer.

Abstract: A common mode filter includes a first iron core, a second iron core, a first coil, and a second coil. The first iron core includes two first electrode portions and two second electrode portions. The second iron core is disposed above the first iron core, and the first iron core and the second iron core are adhered to each other. All surfaces of the second iron core are coated with an insulating layer. The first coil is wound around the first iron core and the second iron core. The second coil is wound around the first iron core and the second iron core.

Abstract: Disclosed in the present disclosure is a method for processing remote sensing images by fusing elevation information.

Abstract: A method, a device and a medium for genome graph analysis based on in-memory computing. The method comprises the following steps: firstly, combining a linear reference genome with genetic variation to construct a genome graph; then, generating indexes for a plurality of vertices of the genome graph, and constructing an index table according to the generated indexes; then dividing the read length into a plurality of substrings with the length of k-mer, and querying the index table to obtain a seed position, generating a reference subgraph according to the seed position, and identifying a candidate mapping position according to the reference subgraph to filter a candidate mapping area; finally, using a PUM mode to run approximate string matching between the read length and all unfiltered candidate mapping positions, so as to complete the optimal alignment of a reference gene sequence and a query gene sequence.

Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Abstract: An installation assembly for a cooking appliance (12) includes a retaining assembly (22) defining a channel (24). The retaining assembly (22) includes a first side arm (104) and a second side arm (106) disposed adjacent to the first side arm (104). The first side arm (104) and the second side arm (106) are biased to a retracted position. A coupling assembly (30) is configured to couple to the cooking appliance (12). The coupling assembly (30) includes a coupling feature (130) having an insertion end (134) and a coupling end (136). A locking feature (140) is coupled to the insertion end (134). The locking feature (140) has a greater width compared to the coupling feature (130) to adjust the first side arm (104) and the second side arm (106) to an extended position as the coupling assembly (30) is inserted through the channel (24). The locking feature (140) is retained on the retaining assembly (22) in an installed position.

Abstract: A display device is provide. The display device is within a transportation device having a first seating area, including a display unit, a mechanical platform, and a mechanical shaft assembly. The mechanical platform is configured to correspond to the first seating area. The mechanical shaft assembly is disposed on the mechanical platform and including a first shaft portion, a second shaft portion, and a third shaft portion. The first shaft portion is connected to the display unit and driving the display unit to move along a horizontal direction. The second shaft portion is connected to an upper end of the display unit and driving the display unit to rotate around a second axis. The third shaft portion is connected to the second shaft portion and driving the display unit to rotate around a third axis.

Abstract: Embodiments of the disclosure relate to a method and apparatus for generating a speech translation model, an electronic device, and a medium. The method includes extracting, by a semantic feature extractor, a source semantic unit sequence of source language audio and a target semantic unit sequence of target language audio, wherein the source language audio corresponds to the target language audio. The method further includes adjusting a first decoder from a plurality of decoders based on the source semantic unit sequence and the target semantic unit sequence. The method further includes adjusting a second decoder of the plurality of decoders based on the source semantic unit sequence, the target semantic unit sequence, a source acoustic unit sequence of the source language audio, and a target acoustic unit sequence of the target language audio.

Abstract: This disclosure relates to a photovoltaic energy storage and power system and a three-phase power control method, apparatus and device for load(s). The three-phase power control method for load(s) in a photovoltaic energy storage and power system includes obtaining a drawing or feeding power of a grid, an charging or discharging power of energy storage, and a photovoltaic generation power; determining a generation power of an electric power system based on the drawing or feeding power of the grid, the charging or discharging power of the energy storage, and the photovoltaic generation power; and distributing the generation power of the electric power system evenly to load(s) of each phase to achieve three-phase dynamic balancing.

Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.

Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may transmit, from a UE to a base station, one or more reference signals over a channel. The UE may receive, from the base station based at least in part on transmitting the one or more reference signals, control signaling indicating a precoding matrix indicator (PMI) and a rank indicator (RI) based at least in part on the UE having at least eight transmit antennas and based at least in part on a phase difference between different subsets of transmit antennas of the at least eight transmit antennas. The UE may transmit, to the base station, an uplink transmission configured according to the PMI and the RI.

Abstract: Embodiments of the present disclosure provide methods and apparatus for tuning a plurality of beams. A method performed at a network node may comprise: determining (S101) a respective coverage requirement for a plurality of beams; determining (S102) a respective coverage area for the plurality of beams, based on the determined coverage requirement; determining (S103) a power requirement for the plurality of beams, based at least on the determined coverage area; and tuning (S104) at least one of the plurality of the beams, based at least on the determined power requirement. The energy efficiency and the network capacity may be improved, while the shape of each beam could be adaptively refactored.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate, a source/drain contact disposed over the substrate, a first dielectric layer disposed on the source drain contact, an etch stop layer disposed on the first dielectric layer, and a source/drain conductive layer disposed in the etch stop layer and the first dielectric layer. The structure further includes a spacer structure disposed in the etch stop layer and the first dielectric layer. The spacer structure surrounds a sidewall of the source/drain conductive layer and includes a first spacer layer having a first portion and a second spacer layer adjacent the first portion of the first spacer layer. The first portion of the first spacer layer and the second spacer layer are separated by an air gap. The structure further includes a seal layer.