Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: The semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, and a second dielectric feature. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner.

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes at least one device on a front side of a semiconductor substrate. A plurality of grating layers are under the at least one device. The plurality of grating layers include at least a first material having a first refractive index alternating with a second material having a second refractive index. Contacts extend through an interlevel dielectric material, and further extend through the semiconductor substrate, to directly contact at least one of the first material and the second material below the at least one device and below the semiconductor substrate underlying the interlevel dielectric material.

Abstract: The present invention provides a composition for a non-therapeutic method for caring for keratin materials. The composition contains in an aqueous phase: (i) at least one cosmetic active compound selected from C-glycosides of formula (I): wherein R represents a saturated C1 to C10, alkyl radical which can optionally be substituted by at least one radical chosen from OH, COOH or COOR?2, with R?2 being a saturated C1-C4 alkyl radical, S represents a monosaccharide or a polysaccharide comprising up to 20 sugar units in pyranose and/or furanose form and of the L and/or D series, and X represents a radical chosen from the —CO—, —CH(OH)—, —CH(NH2)—, —CH(NHCH2CH2CH2OH)—, —CH(NHPh)- and —CH(CH3)— groups, the S—CH2—X bond represents a bond of an ? or ? C-anomeric nature; (ii) at least one surfactant selected from fatty acid esters of polyglycerol; and (iii) at least one surfactant selected from oxyalkylenated fatty acid esters of glycerol.

Abstract: A rack apparatus includes a mother rack including a rectangular platform member, a pivotal left L-shaped support, a pivotal right L-shaped support, a left groove on the platform member, a right groove on the platform member, and a space under the platform member; and a daughter rack including a rectangular platform element, a pivotal left leg, a pivotal right leg, a pivotal limit member disposed on a front end of the platform element, a pivotal surface disposed rearward of the pivotal limit member, a rear support leg having two ends pivotably secured to a back surface of the pivotal surface and the platform element respectively, and a space under the platform element. The left leg may be fastened in the left groove and the right leg may be fastened in the right groove respectively.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed.

Abstract: The present invention provides a geotechnical centrifuge platform-based earthquake fault simulation system, involving the field of earthquake disaster simulation technology. A bottom support system of the geotechnical centrifuge platform-based earthquake fault simulation system is used to support a horizontal actuation system and simulate earthquake faults and site covering layers. The horizontal actuation system is used to apply horizontal thrusts to simulated earthquake faults and site covering layers. The simulated earthquake faults are used to fill fault test blocks to simulate bedrock layers of earthquake faults and the site covering layers are used to fill sand layer materials onto surfaces of the simulated earthquake faults to simulate soil layers of the earthquake faults.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A frequency tripler circuit includes an amplifier to receive a balanced input signal at an input frequency and outputs a balanced signal at a second harmonic of the input frequency. The frequency tripler circuit includes a passive double balanced mixer coupled to an output of the amplifier to receive the balanced signal at the second harmonic and the balanced input signal to generate an output balanced signal having a frequency triple the input frequency.

Abstract: An optical interconnection assembly and method for the deployment and scaling of optical networks employing Spine-and-Leaf architecture has Spine multi-fiber optical connectors and Leaf multi-fiber optical connectors. The Spine optical connectors of the interconnection assembly are optically connected to multi-fiber connectors of Spine switches via Spine patch cords. The leaf multi-fiber connectors are optically connected to Leaf multi-fiber connectors of Leaf switches via Leaf patch cords. A plurality of fiber optic cables in said interconnection assembly serves to optically connect every Spine multi-fiber connector to every Leaf multi-fiber connector so that every Spine switch is optically connected to every Leaf switch. The optical interconnection assembly facilitates the deployment of network Spine-and-Leaf interconnections and the ability to scale out the network by using simplified methods described in this disclosure.

Abstract: Some implementations described herein include techniques and apparatus for forming a semiconductor device including a semiconductor resistor structure. The semiconductor resistor structure (e.g., a low-impedance thin-film resistor structure) may include a resistive layer having an approximately rectangular shape (e.g., a width-to-length ratio that is less than approximately one). The semiconductor resistor structure includes contact structures connected to the resistive layer, a conductive bus structure having an approximately rectangular shape that connects to the contact structures, and an electrical terminal (e.g., a routing pin) centrally located at or near an edge of the conductive bus structure.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.

Abstract: An event processing method is provided, applied to filtering of events in a server. The method includes: matching a to-be-filtered event with an event matching rule, where the event matching rule is used for performing filtering to obtain an event that meets one or more first conditions and one or more second conditions, and the second condition indicates duration or repeatability of the one or more first conditions; and sending an instruction to a destination address when the to-be-filtered event meets the event matching rule. The event processing method provided in this application supports condition rule configuration of duration or repeatability, for example, a timing rule or a count rule.

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.