Patents by Inventor Yu Hui
Yu Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977423Abstract: Methods and systems for thermal management of hardware resources that may be used to provide computer implemented services are disclosed. The disclosed thermal management method and systems may improve the likelihood of data processing systems providing desired computer implemented services by improving the thermal management of the hardware resources without impairment of storage devices. To improve the likelihood of the computer implemented services being provided, the systems may proactively identify whether storage devices subject to impairment due to dynamic motion are present. If such storage devices are present, then the system may automatically take action to reduce the likelihood of the storage devices being subject to dynamic motion sufficient to impair their operation.Type: GrantFiled: December 20, 2021Date of Patent: May 7, 2024Assignee: Dell Products L.P.Inventors: Hung-Pin Chien, Jyh-Yinn Lin, Yu-Wei Chi Liao, Chien Yen Hsu, Ming-Hui Pan
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Publication number: 20240145297Abstract: A structure includes a dielectric layer, and a metal line in the dielectric layer. The metal line has a first straight edge and a second straight edge extending in a lengthwise direction of the metal line. The first straight edge and the second straight edge are parallel to each other. A via is underlying and joined to the metal line. The via has a third straight edge underlying and vertically aligned to the first straight edge, and a first curved edge and a second curved edge connecting to opposite ends of the third straight edge.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yu-Tse Lai, Ya Hui Chang
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Publication number: 20240144056Abstract: A method includes: obtaining impact values for characteristic conditions; selecting training data subsets respectively from training data sets according to the impact values; obtaining a candidate model and an evaluation value based on the training data subsets; supplementing the training data subsets according to the impact values; obtaining another candidate model and another evaluation value based on training data subsets thus supplemented; repeating the step of supplementing the training data subset, and the step of obtaining another candidate model and another evaluation value based on the training data subsets thus supplemented; and selecting one of the candidate models as a prediction model based on the evaluation values.Type: ApplicationFiled: August 2, 2023Publication date: May 2, 2024Applicants: TAIPEI VETERANS GENERAL HOSPITALInventors: Chin-Chou Huang, Ming-Hui Hung, Ling-Chieh Shih, Yu-Ching Wang, Han Cheng, Yu-Chieh Shiao, Yu-Hsuan Tseng
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Patent number: 11973005Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.Type: GrantFiled: August 3, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11968832Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.Type: GrantFiled: October 16, 2020Date of Patent: April 23, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Patent number: 11942532Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chao-Hsuan Chen, Ming-Chia Tai, Yu-Hsien Lin, Shun-Hui Yang, Ryan Chia-Jen Chen
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Patent number: 11943874Abstract: A method of processing component carriers is disclosed. The method includes providing a plurality of arrays each comprising a plurality of component carriers, providing a plurality of separator bodies, forming an alternating stack of the arrays and the separator bodies so that each adjacent pair of stacked arrays is spaced by a respective separator body, and carrying out at least one process, in particular at least one back-end process, using the stack. A separator sheet for spacing arrays and a method of using separator sheets for spacing arrays during processing the arrays are also provided.Type: GrantFiled: December 11, 2020Date of Patent: March 26, 2024Assignee: AT&S (Chongqing) Company LimitedInventors: Amin Nickkolgh, Yu-Hui Wu, Ismadi Bin Ismail
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Patent number: 11940658Abstract: An optical fiber module is provided and includes an optical fiber structure, a light-absorbing area and a photoelectric sensor in a housing. The optical fiber structure collectively arranges a plurality of first optical fibers to form at least one optical fiber bundle with a tapered end, and a second optical fiber is connected to the tapered end of the optical fiber bundle to converge the optical fiber bundle to the second optical fiber. The light-absorbing area corresponds to an end of the second optical fiber, such that the light-absorbing area absorbs scattering signals escaped and scattered when signals are transmitted from the plurality of first optical fibers to the second optical fiber. The photoelectric sensor is arranged corresponding to the plurality of first optical fibers to receive target signals escaped and refracted when the signals are transmitted from the second optical fiber to the plurality of first optical fibers.Type: GrantFiled: December 22, 2021Date of Patent: March 26, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsin-Chia Su, Ying-Hui Yang, Yu-Cheng Song, Tsung-Jun Ho
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Publication number: 20240097662Abstract: An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Yu-Kai TSAI, Chia-Hui CHEN, Chia-Jung CHANG
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Patent number: 11923352Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.Type: GrantFiled: January 28, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsin-Li Cheng, Shu-Hui Su, Yu-Chi Chang, Yingkit Felix Tsui, Shih-Fen Huang
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Patent number: 11923437Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: GrantFiled: October 25, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11924964Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.Type: GrantFiled: April 7, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Lin Hui Chen, Songtao Lu, Chien Te Chen, Yu Ying Tan, Huang Pao Yi, Ching Chuan Hsieh, T. Sharanya Kaminda, Chia-Hsuan Huang
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Patent number: 11921552Abstract: A computer chassis includes walls defining an airspace containing heat-generating components (e.g., storage drives). The airspace is divided into first and second regions, such as by a printed circuit board supporting the heat-generating components within the first region. An air input feeds both the first region and second region. Input air going through the first region first passes by a forward set of heat-generating components before continuing to a rearward set of heat-generating components to extract heat therefrom. Input air going through the second region bypasses the forward set of heat-generating components before being directed out through an air opening partway down the length of the chassis, after which this air passes by a rearward set of heat-generating components to extract heat.Type: GrantFiled: May 26, 2022Date of Patent: March 5, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chao-Jung Chen, Yu-Nien Huang, Jen-Hui Wang
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Patent number: 11912006Abstract: A continuous manufacturing equipment of an elastic three-dimensional fabric and a continuous manufacturing method thereof are disclosed. The continuous manufacturing equipment includes: a film conveying device having a thermal melting film and a conveying mechanism; a cutting device used for cutting a plurality of cutting gaps on the thermal melting film; a first fabric laminating device adhering an outer fabric on one surface of the thermal melting film; and a second fabric laminating device adhering an elastic fabric on another surface of the thermal melting film in a manner of elastically stretching and then elastically recovering. As such, effects of automatic, continuous, and simple steps in manufacturing and having a high yield rate are provided.Type: GrantFiled: May 10, 2022Date of Patent: February 27, 2024Assignee: TAIWAN TEXTILE FEDERATION, R.O.C.Inventors: Shu-Hui Huang, Hung-Kung Chien, Yu-Han Tsai
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Patent number: 11868018Abstract: Disclosed are an electrochromic element, device, and product, and a manufacturing method therefor. The electrochromic device (7) comprises: an electrochromic yarn (6), an ion storage yarn (18), and a power source (8), wherein the electrochromic yarn (6) contains a first flexible conductive yarn (5) and an electrochromic layer (4) coated on a surface layer of the first flexible conductive yarn (5); the ion storage yarn (18) contains a second flexible conductive yarn (1) and an ion storage layer (17) coated on a surface layer of the second flexible conductive yarn (1); and the first flexible conductive yarn (5) is electrically connected to a negative electrode of the power source (8), and the second flexible conductive yarn (1) is electrically connected to a positive electrode of the power source (8). The electrochromic device (7) can achieve a clear color development effect and make an electrochromic material have a good fastness.Type: GrantFiled: April 10, 2018Date of Patent: January 9, 2024Assignee: THE HONG KONG RESEARCH INSTITUTE OF TEXTILES AND APPAREL LIMITEDInventors: Edwin Yee Man Keh, Lei Yao, Yeung Yu Hui, Xinxin Huang, Yue Kit Hui, Colin Xin Chen, Derek Lai
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Patent number: 11832057Abstract: A piezoelectric microelectromechanical systems microphone can be mounted on a printed circuit board. The microphone can include a substrate with an opening between a bottom end of the substrate and a top end of the substrate. The microphone can include a single piezoelectric film layer disposed over the top end of the substrate and defining a diaphragm structure, the single piezoelectric film layer having substantially zero residual stress and formed from a piezoelectric wafer. The microphone can include one or more electrodes disposed over the diaphragm structure. The diaphragm structure is configured to deflect when subjected to sound pressure via the opening in the substrate.Type: GrantFiled: December 12, 2022Date of Patent: November 28, 2023Assignee: Skyworks Solutions, Inc.Inventors: Yu Hui, Guofeng Chen
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Publication number: 20230376977Abstract: A computer implemented method, system and non-transitory medium for predicting whether a new customer of one or more insurance products will purchase an additional insurance product. Training data associated with a set of customers is collected, and a dataset generated containing customers who have made two or more insurance purchases. Data fields are extracted using a sequential marked basket analysis algorithm and multiple augmented training data sets using different encoding techniques generated therefrom. Data fields are extracted from each augmented data set using a feature extraction algorithm. A plurality of models are trained on the extracted data fields and values with the performance of each trained model on a combination of the augmented data sets evaluated. The output of each trained model is weighted according to the determined model performance and used to predict the likelihood of a new customer to purchase an additional insurance product.Type: ApplicationFiled: June 30, 2022Publication date: November 23, 2023Applicant: Valdimir Pte. Ltd.Inventors: Yu Hui Yao, Xu Cheng
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Publication number: 20230378044Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.Type: ApplicationFiled: February 14, 2023Publication date: November 23, 2023Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chun-Ting Kuo, Yu-Hui Hu, Chih-Hao Chiang, Chen-Yu Wang, Kung-An Lin, Pai-Sheng Cheng
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Patent number: 11775874Abstract: Techniques for generating and evaluation predictive models to optimize computing applications are described herein. In some embodiments, a system generates, using a model, a first set of scores for a plurality of accounts, wherein a score in first set of scores for a respective account characterizes a priority of interacting with the respective account relative to other accounts in the plurality of accounts, wherein the model defines a set of criteria for scoring accounts, wherein each criterion in the set of criteria is associated with one or more feature values and a weight. The system may receive user input that modifies the set of criteria. Responsive to the user input the system may update the model and generate, using the updated model, a second set of scores for the plurality of accounts. Actions may be prioritized/executed based at least in part on the account scores.Type: GrantFiled: May 19, 2020Date of Patent: October 3, 2023Assignee: Oracle International CorporationInventors: Andrew Kiang, Yu-Hui Huang