Patents by Inventor Yu Jen Chen
Yu Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136346Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.Type: ApplicationFiled: April 17, 2023Publication date: April 25, 2024Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
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Publication number: 20240136317Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
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Publication number: 20240136383Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Publication number: 20240128341Abstract: The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.Type: ApplicationFiled: December 14, 2022Publication date: April 18, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chia-Hao Chang, Jih-Wen Chou, Hwi-Huang Chen, Hsin-Hong Chen, Yu-Jen Huang
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Patent number: 11961810Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.Type: GrantFiled: June 21, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
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Publication number: 20240119200Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Applicant: MEDIATEK INC.Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
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Publication number: 20240119875Abstract: A mending method for a display includes the steps of making a display device light to make a plurality of light emitting positions thereof shine, searching out a plurality of defect positions among the light emitting positions, providing a transferring device having a transferring surface with a plurality of miniature light emitting elements positioned correspondingly to the light emitting positions, planning a mending procedure which includes in the area the transferring surface corresponds to, choosing in chief the largest number of defect positions able to be mended at a single time according to the positions of the miniature light emitting elements and then in the area the transferring surface corresponds to, planning the rest of the defect positions according to the rest of the miniature light emitting elements, and according to the mending procedure, moving the transferring device to weld the miniature light emitting elements at the defect positions.Type: ApplicationFiled: October 5, 2023Publication date: April 11, 2024Inventors: Tsan-Jen CHEN, Chih-Hao TSAI, Yu-Cheng YANG, Jen-Hung Lo, Yan-Ru TSAI
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Publication number: 20240102194Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.Type: ApplicationFiled: August 7, 2023Publication date: March 28, 2024Inventors: Cheng-EN HO, Yu-Lian CHEN, Cheng-Chi WANG, Yu-Jen CHANG, Yung-Sheng LU, Cheng-Yu LEE, Yu-Ming LIN
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Publication number: 20240100352Abstract: A phototherapy device includes a base, at least one light conversion device and a light source module. The base has an installation slot. The light conversion device is detachably arranged in the installation slot. Each light conversion device includes a plurality of light conversion patterns. The light source module is arranged on a side of the base and configured to provide an excitation beam to the light conversion patterns, so that each of the light conversion patterns emits a converted beam. In this way, the light conversion device of the phototherapy device can be replaced according to the user's needs.Type: ApplicationFiled: September 19, 2023Publication date: March 28, 2024Inventors: CHUNG-JEN OU, YU-MIN CHEN, MING-WEI TSAI, CHIEN-CHIH CHEN
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Publication number: 20240103292Abstract: An attached floating image touch-control device is provided. The attached floating image touch-control device includes a trigger module, a floating image generation module and a sensing module. The trigger module includes a movable trigger component. The floating image generation module includes a light source, an imaging unit, and a floating imaging unit disposed on the imaging unit. The sensing module is arranged on the floating image generation module and communicatively connected to the trigger module, wherein when the sensing module senses a touch action, the sensing module outputs a driving signal, and the trigger module moves the trigger component based on the driving signal to contact and trigger the contact-type button.Type: ApplicationFiled: August 21, 2023Publication date: March 28, 2024Inventors: RAN-SHIOU YOU, YA HAN KO, YU JEN LAI, HSING-YU CHEN
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20240090190Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Publication number: 20240088026Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.Type: ApplicationFiled: January 17, 2023Publication date: March 14, 2024Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
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Publication number: 20240072129Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Chih-Jung Chen, Yu-Jen Yeh
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Publication number: 20240007302Abstract: A data verification system comprises a provider-end computer apparatus and a request-end computer apparatus. The provider-end computer apparatus is configured to: receive a request of data from the request-end computer apparatus; retrieve a data cluster designated in the request of data; execute a first fingerprint process on an unrequested part of the data cluster, which includes everything in the data cluster other than a requested part so as to obtain an unrequested data fingerprint; and return the requested part of the data cluster and the unrequested data fingerprint to the request-end computer apparatus.Type: ApplicationFiled: September 18, 2023Publication date: January 4, 2024Inventors: NAI-HO HSU, CHI-KUANG LEE, YU-JEN CHEN
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Publication number: 20230409096Abstract: A power supply system includes a plurality of power modules for supplying power to a load, and each power module provides an output current according to a modulation signal, and provides the output current to a power bus through an output end and supply the output current to the load through the power bus. Each power module is connected to a common-connected point of a signal bus to generate a second voltage level, acquires a first ratio according to a full-load output power of the conversion circuit corresponding to the controller and the full-load output power of the power module capable of outputting the maximum power, adjusts the first voltage level according to the first ratio and the second voltage level to adjust the amplified signal by adjusting the first voltage level, and adjusts the output current to a target value corresponding to the first ratio by adjusting the amplified signal.Type: ApplicationFiled: December 7, 2022Publication date: December 21, 2023Inventors: Chin-Pin CHEN, Yu-Jen CHEN
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Patent number: 11844205Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.Type: GrantFiled: February 21, 2023Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
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Publication number: 20230385508Abstract: A semiconductor structure includes first and second active regions extending in a first direction. The semiconductor structure further includes gate electrodes extending in a second direction perpendicular to the first direction. Each of the gate electrodes includes a first segment over at least one of the first active region or the second active region; a gate extension extending beyond each of the first active region and the second active region, wherein the gate extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the gate extension increases along an entirety of the conductive element in the second direction.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Patent number: 11810934Abstract: An image sensor is provided. The image sensor includes a substrate having a first pixel region and a second pixel region. The image sensor also includes a resonator structure disposed over the substrate. The resonator structure includes a first metal layer over the first pixel region and the second pixel region. The resonator structure also includes a first insulating layer over the first metal layer and the first pixel region. The first insulating layer has a first thickness. The resonator structure further includes a second insulating layer over the first metal layer and the second pixel region. The second insulating layer has a second thickness that is greater than the first thickness. In addition, the resonator structure includes a second metal layer over the first insulating layer and the second insulating layer.Type: GrantFiled: April 3, 2018Date of Patent: November 7, 2023Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Yu-Jen Chen, Chang-Wei Chen
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Publication number: 20230337971Abstract: A detecting method for a behavior disorder event during rapid-eye-movement sleep is provided. The detecting method includes: collecting a heart rate value and a motion value of a user per epoch within a time period; generating a plurality of corresponding sleep condition values by using the motion values, to distinguish epochs into an awake period and a sleep period; transforming the motion values corresponding to the sleep period into a score according to a predetermined rule, to generate a plurality of sleep depth scores, and distinguishing the sleep period into a light sleep period and a deep sleep period by using the sleep depth scores; grouping the heart rate values corresponding to the deep sleep period as a high heart rate group and a low heart rate group; and determining, when the motion values corresponding to the high heart rate group satisfy a condition, that a behavior disorder event happens.Type: ApplicationFiled: October 31, 2022Publication date: October 26, 2023Inventors: Pei-Chi CHUANG, Chun-Hsiang TSAI, Yu-Jen CHEN, Ching-Fu WANG, Shih-Zhang LI, Sheng-Huang LIN, Pei-Hsin KUO, You-Yin CHEN