Patents by Inventor Yu Jen Chen

Yu Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12253506
    Abstract: A method of building upstream-and-downstream configuration of sensors includes determining two sets of geographic position data of a target sensor and a candidate sensor, obtaining pollution-associated periods according to pieces of flow field data, the sets of geographic position data and pieces of target sensing data of the target sensor to determine a pollution-associated period, calculating a correlation between target sensing data obtained by the target sensor during the pollution-associated period and candidate sensing data obtained by the candidate sensor during the associated air pollution period to obtain sensor correlations, and determining the target sensor and the candidate sensor having a upstream-and-downstream relationship with the candidate sensor being used as a satellite sensor of the target sensor when a quantity ratio of sensor correlations being larger than or equal to a correlation threshold is larger than or equal to a default ratio.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: March 18, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin Wang, Guang-Huei Gu, Chih-Jen Chen
  • Publication number: 20250084172
    Abstract: The present disclosure relates to a ULBP6 binding protein that inhibits the interaction between ULBP6 and NKG2D, and methods of treating cancer with said ULBP6 binding protein.
    Type: Application
    Filed: July 15, 2024
    Publication date: March 13, 2025
    Applicants: 23andMe, Inc., Glaxosmithkline Intellectual Property (No.3) Ltd
    Inventors: Joel Benjamin, Shashank Bharill, I-Ling Chen, Yu Chen, Wei-Jen Chung, Zahra Bahrami Dizicheh, Germaine Fuh, Patrick Koenig, Yujie Liu, Mauro Poggio, Shruti Yadav, Ping-Chiao Tsai, Claus Spitzfaden
  • Publication number: 20250077219
    Abstract: The present disclosure discloses an electronic system having firmware forward and backward compatibility mechanism. A read-only storage circuit stores first version firmware. A processing circuit configured to store the first version firmware from the read-only storage circuit to a readable and writable storage circuit to perform a system initialization, determine a version of second version firmware included in a driver received from a driver storage terminal is earlier than the first version firmware, merge a variable function having a first version content in the first version firmware and the variable function having a second version content in the second version firmware, replace a first version function pointer in the first version firmware by a second version function pointer in the second version firmware to generate updated firmware having a updated share data section and perform function call according to the updated share data section to continue performing system initialization.
    Type: Application
    Filed: August 29, 2024
    Publication date: March 6, 2025
    Inventor: YU-JEN CHEN
  • Publication number: 20250079177
    Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.
    Type: Application
    Filed: November 7, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Ping LIN, Yu-Ling KO, I-Chung WANG, Yi-Jen CHEN, Sheng-Kai JOU, Chih-Teng LIAO
  • Patent number: 12237402
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
  • Patent number: 12237415
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Patent number: 12230595
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Publication number: 20250053821
    Abstract: An auto-regressive method for a large language model includes receiving a hidden state associated with at least one token, generating key data, first value data, and query data according to a received hidden state, generating first positionally encoded key data by encoding the key data positionally, generating positionally encoded query data by encoding the query data positionally, performing first element-wise dot product operations according to the first positionally encoded key data, the positionally encoded query data, and second positionally encoded key data to generate an attention score, performing second element-wise dot product operations according to the first value data, the attention score, and second value data to generate an attention output, and adding the attention output and the hidden state to generate an updated hidden output.
    Type: Application
    Filed: July 11, 2024
    Publication date: February 13, 2025
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Jia Yao Christopher LIM, Kelvin Kae Wen TEH, Po-Yen LIN, Jung Hau FOO, Chia-Wei HSU, Yu-Lung LU, Hung-Jen CHEN, Chung-Li LU, Wai Mun WONG
  • Patent number: 12223123
    Abstract: Disclosed herein are teeth-operated mouth mouses and methods of using the same. In some embodiments, the teeth-operated mouth mouse includes a mounting conforming to a row of upper teeth in the oral cavity of a user; and a plurality of sensors independently disposed at a position corresponding to an individual tooth along the mounting and wirelessly coupled to the computer for transmitting and receiving signals therebetween; wherein, each of the plurality sensors is capable of performing at least one teeth-activating task selected from the group consisting of “moving to the right”, “moving to the left”, “moving forward”, “moving backward”, and “enter”. Also provided herein are methods of operating a computer with the aid of the disclosed teeth-operated mouth mouse.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: February 11, 2025
    Assignee: Mackay Memorial Hospital
    Inventor: Yu-Jen Chen
  • Patent number: 12216326
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 4, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiang-Chin Lin, Shou-Jen Liu, Guan-Bo Wang, Kai-Po Fan, Chan-Jung Hsu, Shao-Chung Chang, Shih-Wei Hung, Ming-Chun Hsieh, Wei-Pin Chin, Sheng-Zong Chen, Yu-Huai Liao, Sin-Hong Lin, Wei-Jhe Shen, Tzu-Yu Chang, Kun-Shih Lin, Che-Hsiang Chiu, Sin-Jhong Song
  • Patent number: 12211876
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 12205906
    Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: January 21, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Yuan-Hung Hsu, Chi-Jen Chen
  • Publication number: 20240415859
    Abstract: The invention relates to a new use of Isorhoifolin and its derivatives. The invention provides uses of the Isorhoifolin derivatives for promoting regeneration of injured brain neurons and retinal neurons.
    Type: Application
    Filed: October 25, 2022
    Publication date: December 19, 2024
    Inventors: Linyi CHEN, Yu-Jen CHEN
  • Publication number: 20240404889
    Abstract: A non-active gate structure is formed over a shallow trench isolation (STI) region that is adjacent to at least one fin structure of a semiconductor device that includes a fin-based transistor. The non-active gate structure includes at least one support structure that extends from the gate in a direction that is approximately orthogonal to the direction in which the main body of the non-active gate structure extends. The support structure provides structural support for the non-active gate structure, which increases the stability of the non-active gate structure relative to a gate structure that does not include the support structure.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Inventors: Shih-Sian TU, Yu-Jen CHEN, Jhen-Wei CHEN
  • Publication number: 20240387366
    Abstract: Disclosed are methods of manufacturing semiconductor devices that include the operations of forming an isolation structure in a semiconductor substrate, forming an active region adjacent the isolation structure, forming at least two primary polysilicon structures over the active region, the primary polysilicon structures defining a contacted polysilicon pitch (CPP), and forming a secondary polysilicon structure over the isolation structure. In some methods, the secondary polysilicon structure is further modified and/or replaced in order to provide additional functional elements on the semiconductor devices.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Inventors: Yi-Ming LIN, Jhen-Wei CHEN, Ling-Sung WANG, Yu-Jen CHEN
  • Publication number: 20240389445
    Abstract: A method of reducing splicing spacing of an OLED display panel splicing unit includes the steps of: A) preparing: preparing a semi-finished splicing unit having a substrate, the substrate having thereon a plurality of wires, a plurality of light-emitting components, a plurality of edge connecting pads, at least one baffle and a transparent gum; B) cutting: cutting off a portion of the substrate, with the portion cut off at least lying outside the at least one baffle, leaving intact at least the plurality of wires, the plurality of light-emitting components, the plurality of edge connecting pads and the transparent gum on the substrate; and C) partial degumming: removing a portion of the transparent gum to allow the plurality of edge connecting pads to be partially exposed and not covered with the transparent gum.
    Type: Application
    Filed: June 16, 2023
    Publication date: November 21, 2024
    Inventor: Yu-Jen CHEN
  • Publication number: 20240387487
    Abstract: A display panel splicing unit and a display panel spliced by the display panel splicing unit are provided. The display panel splicing unit has a splicing unit and a double-sided circuit substrate. The splicing unit has a transparent splicing board and a plurality of light-emitting components disposed on the transparent splicing board to emit light penetrating the transparent splicing board and thus traveling downward. The double-sided circuit substrate is not a printed circuit board (PCB) but is made of glass or ceramic and has a plurality of connecting elements for connecting wires on upper and lower surfaces of the double-sided circuit substrate, allowing a controller to be mounted thereon. Two splicing units share one double-sided circuit substrate and thus can be controlled with just one controller, allowing a display panel to be formed by splicing, using a small number of controllers.
    Type: Application
    Filed: June 16, 2023
    Publication date: November 21, 2024
    Inventor: Yu-Jen CHEN
  • Publication number: 20240379628
    Abstract: A splicing unit for display panels includes: a splicing board having an upper surface on which a plurality of main wires are disposed and at least one lateral surface defined as a splicing surface; a lead board having a lower surface on which a plurality of lead wires are disposed, at least one lateral surface defined as a lead splicing surface being flush with the splicing surface substantially, and an upper surface attached to a lower surface of the splicing board; and a plurality of bridging wires each having one end connected to one of the main wires and positioned proximate to the upper surface of the splicing board, a body extending and crossing the splicing surface and the lead splicing surface, and the other end connected to one of the lead wires and positioned proximate to the lower surface of the lead board.
    Type: Application
    Filed: June 16, 2023
    Publication date: November 14, 2024
    Inventor: Yu-Jen CHEN
  • Publication number: 20240288950
    Abstract: Disclosed herein are teeth-operated mouth mouses and methods of using the same. In some embodiments, the teeth-operated mouth mouse includes a mounting conforming to a row of upper teeth in the oral cavity of a user; and a plurality of sensors independently disposed at a position corresponding to an individual tooth along the mounting and wirelessly coupled to the computer for transmitting and receiving signals therebetween; wherein, each of the plurality sensors is capable of performing at least one teeth-activating task selected from the group consisting of “moving to the right”, “moving to the left”, “moving forward”, “moving backward”, and “enter”. Also provided herein are methods of operating a computer with the aid of the disclosed teeth-operated mouth mouse.
    Type: Application
    Filed: June 22, 2021
    Publication date: August 29, 2024
    Inventor: Yu-Jen CHEN
  • Patent number: D1065452
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: March 4, 2025
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Yu-Chien Yang, Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai