Patents by Inventor Yu Jen Chen

Yu Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210363283
    Abstract: A resin composition, a light conversion layer and a light emitting device are provided. The resin composition includes a quantum dot (A), an alkali-soluble resin (B), an ethylenically unsaturated monomer (C), a photoinitiator (D), a solvent (E) and a phenyl-based compound (F). The phenyl-based compound (F) includes at least one of a compound represented by following Formula (F-1) and a compound represented by following Formula (F-2). Based on a total usage amount of the resin composition as 100 parts by weight, a usage amount of the phenyl-based compound (F) is 0.05 to 5 parts by weight. In Formula (F-1) and Formula (F-2), the definition of R1, R3, R4, Y, Z, m, n and p are the same as defined in the detailed description.
    Type: Application
    Filed: April 23, 2021
    Publication date: November 25, 2021
    Applicant: eChem Solutions Corp.
    Inventors: Hsiao-Jen Lai, Yu-Chun Chen
  • Patent number: 11183090
    Abstract: A test circuit and a test method for display panels are provided. The test circuit comprises: switch units; first test leads; first test pads; and a second test pad, a second test lead, a third test pad and a switch control line. Numbers of the switch units, the first test leads and the first test pads are the same; each of the first test leads is electrically connected to a corresponding one of the display panels; each of the first test pads is electrically connected to an output terminal of the corresponding switch unit, and each of the first test pads is electrically connected to the corresponding first test lead; the second test pad and the second test lead are electrically connected to input terminals of the switch units; and the third test pad and the switch control line are electrically connected to control terminals of the switch units.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: November 23, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Publication number: 20210358816
    Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
  • Patent number: 11177308
    Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
  • Patent number: 11174363
    Abstract: A method of preparing a thermoplastic polyurethane membrane with high adhesion and high elasticity includes the following steps: (a) preparing a modifying solution, wherein the modifying solution is one or a mixture of at least two of diethylenetriamine, diethylaminopropylamine, and diaminodiphenylmethane; (b) preparing a semi-finished product by applying the modifying solution on at least one surface of a thermoplastic polyurethane membrane; and (c) subjecting the semi-finished product to a temperature of 50° C.˜180° C. in order for the semi-finished product to undergo a reaction and thus form the thermoplastic polyurethane membrane with high adhesion and high elasticity.
    Type: Grant
    Filed: June 16, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN TEXTILE FEDERATION, R.O.C.
    Inventors: Shu-Hui Huang, Sheng-Jen Lin, Yao-Hung Kuo, Jian-Fan Chen, Hung-Kung Chien, Yu-chuan Lin, Yun-chin Kuo
  • Publication number: 20210351139
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Patent number: 11171109
    Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Po Chih Yang, Yu Jen Chen, Po Chen Kuo, Shih Wei Liang
  • Publication number: 20210341843
    Abstract: A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Su-Yu Yeh, Li-Jen Wu, Zhi-You Ke, Ming-Hung Lin
  • Publication number: 20210334751
    Abstract: A shipment prediction method and a shipment prediction device using the shipment prediction method obtains name of at least one material or product or object, and at least one number corresponding to the material name; a pre-trained material consumption prediction model is invoked, and consumption or usage of such material corresponding to the at least one number. A correspondence relation table between material numbers and product information is queried according to the quantities of material corresponding to the at least one number, and a shipment or dispatch of materials corresponding to the at least one number. The correspondence relation table records material numbers of all materials required for producing each product and a quantity of materials for each product and overall. The shipment prediction method and device renders shipment prediction more efficient and effective.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 28, 2021
    Inventors: KAI-HSUN HSUEH, LI-MING CHEN, YU-JEN CHANG, SHANG-YI LIN
  • Patent number: 11158225
    Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 26, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Wei-Chien Liao, Yu-Jen Chen, Meng-Chieh Tsai
  • Patent number: 11158222
    Abstract: A test circuit and a test method for display panels, the test circuit comprising: switch units, first test leads, first test pads, a second test pad and a second test lead; wherein numbers of the switch units, the first test leads and the first test pads are the same; each of the first test leads is configured to be electrically connected to a corresponding one of the display panels; each of the first test pads is electrically connected to an output terminal of the corresponding switch unit, and each of the first test pads is electrically connected to the corresponding first test lead; the second test pad and the second test lead are electrically connected to an input terminals of the switch units.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 26, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-jen Chen
  • Publication number: 20210327945
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
  • Publication number: 20210327951
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Y.L. Yang
  • Patent number: 11152451
    Abstract: A display panel and a display device are provided. The display panel includes a substrate, a plurality of signal lines, a plurality of fan-out lines, and a resistance balance member. The substrate defines a display area and a fan-out area. The signal lines are defined in the display area, and the fan-out lines are defined in the fan-out area and are electrically communicated with the signal lines. The fan-out area defines a central winding line region and a peripheral straight line region. The resistance balance member is connected to one fan-out line of the peripheral straight line region in series.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 19, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 11146056
    Abstract: An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: October 12, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yu-Jen Cheng, Chih-Wei Mu, Sheng-Tsung Chen, Chieh-Min Lo, Wei-Chung Chang
  • Publication number: 20210313287
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20210305261
    Abstract: A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut fl
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Publication number: 20210302690
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: Hsiang-Chin LIN, Shou-Jen LIU, Guan-Bo WANG, Kai-Po FAN, Chan-Jung HSU, Shao-Chung CHANG, Shih-Wei HUNG, Ming-Chun HSIEH, Wei-Pin CHIN, Sheng-Zong CHEN, Yu-Huai LIAO, Sin-Hong LIN, Wei-Jhe SHEN, Tzu-Yu CHANG, Kun-Shih LIN, Che-Hsiang CHIU, Sin-Jhong SONG
  • Publication number: 20210296989
    Abstract: A switching regulator which has load transient quick response ability includes at least one power stage circuit and a control circuit. The control circuit includes a pulse width modulation (PWM) signal generation circuit and a quick response (QR) signal generation circuit. The PWM signal generation circuit generates a PWM signal according to an output voltage and a QR signal, to control a power switch of the corresponding power stage circuit, thus converting an input voltage to the output voltage. The QR signal generation circuit includes a differentiator circuit and a comparison circuit. The differentiator circuit performs a differential operation on a voltage sensing signal related to the output voltage, to generate a differential signal. The comparison circuit compares the differential signal with a QR threshold signal, such that when the differential signal exceeds the QR signal, the PWM signal generation circuit performs a QR procedure.
    Type: Application
    Filed: January 11, 2021
    Publication date: September 23, 2021
    Inventors: Yung-Jen Chen, Yu-Chieh Lin, Chia-Chi Liu, Fu-To Lin
  • Patent number: 11126045
    Abstract: A curved display panel and a display device. The curved display panel (400) includes a substrate; the substrate includes a pixel region, an integrated circuit region, and a fan-out region located between the pixel region and the integrated circuit region. The pixel region includes signal lines. The integrated circuit region includes an integrated circuit driver. A driving chip is provided in the integrated circuit driver. The fan-out region includes a fan-out line. The wiring parameters of the fan-out line and the signal line change along with the change of a target curvature of the substrate where the fan-out line and the signal line are located.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 21, 2021
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Yu-Jen Chen