Abstract: A semiconductor device includes a plurality of interlayer dielectric layers, a memory cell, and a first capping layer. The memory cell is embedded in the interlayer dielectric layers, the first capping layer covers the memory cell and surrounds the sidewalls of the memory cell, the first capping layer includes a hydrogen absorbing material, and the hydrogen absorbing material prevents hydrogen gas from entering the memory cell.

Abstract: A method for adjusting application settings is provided. The method includes using an application setting module to receive at least one performance target from an application running on an electronic device. The method further includes using the application setting module to record at least one performance indicator of the application while the application is running, wherein the performance indicator corresponds to the performance target. The method further includes using the application setting module to estimate the estimated time that the temperature of the electronic device sustains less than the defense temperature. The method further includes using the application setting module to determine the score according to the performance indicator and the estimated time, wherein the score indicates to the application that it should raise, lower, or keep a current setting.

Abstract: A method for decolorizing a polyester fabric is provided, which includes: providing a dyed polyester fabric, in which a material of the dyed polyester fabric contains a dye and a water repellent; providing a composite solvent, in which the composite solvent includes propylene glycol methyl ether (PM) and acetic acid that are mixed together; and performing an extraction process, which includes using the composite solvent to wet the dyed polyester fabric and remove the dye and the water repellent from the material of the polyester fabric by extraction, so as to obtain a reduced polyester fabric.

Abstract: A force sensing device is mounted on a tool to sense force, particularly quasi-static and static forces. The force sensing device includes at least one a sensor. A piezoelectric element in the sensor includes a driving portion and a sensing portion. A first voltage is input to the driving portion to generate a vibration in the piezoelectric element and a second voltage in response to the vibration is output from the sensing portion. The second voltage output from the sensing portion is changed as the vibration in the piezoelectric element is suppressed by an external force acting on the force sensing device so variation of the second voltage can be used to measure the external force.

Abstract: A method for improving hue of recycled bis-2-hydroxylethyl terephthalate by using ionic liquids including providing a recycled polyester fabric; using a chemical de-polymerization liquid to chemically de-polymerize the recycled polyester fabric to form a de-polymerization product; mixing the de-polymerization product with water to form an aqueous phase liquid; dispersing an ionic liquid impurity adsorption material into the aqueous phase liquid to adsorb impurities originally present in the recycled polyester fabric.

Abstract: A dual mode charge control method includes steps of: detecting an input voltage of the resonance tank, a resonance current of the resonance tank, an output current of the load, and an output voltage of the load; performing a single-band charge control when determining a light-load condition or a no-load condition of the load according to the output current; compensating the output voltage to generate an upper threshold voltage in the single-band charge control, and acquiring a resonance voltage by calculating the resonance current by a resettable integrator; comparing the resonance voltage and the upper threshold voltage to generate a first control signal; generating a second control signal complementary to the first control signal by a pulse-width modulation duplicator; providing the first control signal and the second control signal to respectively control a first power switch and a second power switch of the resonance circuit.

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: A method of recycling polyester fabric includes following steps. A polyester fabric including polyethylene terephthalate and dyes is provided. An extraction process including using ethylene glycol as an extraction solvent, immersing the polyester fabric in the extraction solvent, and extracting under a temperature of 80° C. to 180° C. is performed to remove the dyes from the polyester fabric. A depolymerization process including using a chemical depolymerization solution to depolymerize the polyester fabric treated with the extraction process to obtain a product including BHET is performed. The chemical depolymerization solution is ethylene glycol. A purification process is performed to remove impurities of the product obtained by the depolymerization process and to obtain a purified BHET. A solvent recycling process is performed.

Abstract: A novel rheology modifier which comprises a quaternary ammonium containing polyamide for use in aqueous paint, and that can provide excellent pigment suspension and rheological properties to the aqueous based coating without being affected by pH fluctuation.

Abstract: An optical system includes a pancake lens assembly and a varifocal lens device. The varifocal lens device is coupled to the pancake lens assembly in a way that an optical axis of the varifocal lens device is in alignment with an optical axis of the pancake lens assembly, thereby permitting the optical system to have an adjustable focal length.

Abstract: A driving mechanism is provided for moving an optical element, including a fixed module, a movable module holding the optical element, a driving assembly for driving the movable module to move relative to the fixed module, a position-sensing element, and a 3D circuit. The fixed module has a base, and the position-sensing element is disposed on the base to detect the movement of the movable module relative to the fixed module. The 3D circuit is embedded in the base and electrically connected to the position-sensing element.

Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.

Abstract: This disclosure provides a semiconductor structure and a method of forming buried field plate structures. The semiconductor structure includes a substrate, buried field plate structures, and a gate. The substrate incudes a first surface and a second surface opposite the first surface. Each of the buried field plate structures include a conductive structure and an insulation structure surrounding the conductive structure. The gate is embedded in the substrate and extend into the substrate from the first surface of the substrate, wherein the gate is configured between the two neighboring buried field plate structures. The conductive structure includes portions arranging along a direction perpendicular to the first surface of the substrate and having different widths in a direction parallel to the first surface of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

Abstract: A GaN device with N2 pre-treatment is provided in the present invention, including a GaN substrate, an AlGaN layer covering the GaN substrate, a p-GaN gate on the AlGaN layer, a TiN electrode on the p-GaN gate, a first dielectric layer on the AlGaN layer surrounding the p-GaN gate, wherein a horizontal spacing is between the first dielectric layer and the p-GaN gate, and an interface between the AlGaN layer and the GaN substrate not covered by the first dielectric layer is subject to N2 pre-treatment, and a second dielectric layer covering on and directly contacting the exposed first dielectric layer, AlGaN layer, p-GaN gate and TiN electrode.

Abstract: A HEMT device including a substrate structure, a channel layer, a barrier layer, a gate electrode, a drain electrode, a first source field plate, a second source field plate, and a dielectric structure is provided. The first source field plate extends from the second side of the gate electrode to the first side of the gate electrode. The second source field plate is located on the first side of the gate electrode and is located between the drain electrode and the first source field plate. There is a gap between the first source field plate and the second source field plate. The first source field plate has an end adjacent to the gap. The thickness of the dielectric structure located directly below the second source field plate is greater than the thickness of the dielectric structure located directly below the end of the first source field plate.