Abstract: This disclosure provides a semiconductor structure and a method of forming buried field plate structures. The semiconductor structure includes a substrate, buried field plate structures, and a gate. The substrate incudes a first surface and a second surface opposite the first surface. Each of the buried field plate structures include a conductive structure and an insulation structure surrounding the conductive structure. The gate is embedded in the substrate and extend into the substrate from the first surface of the substrate, wherein the gate is configured between the two neighboring buried field plate structures. The conductive structure includes portions arranging along a direction perpendicular to the first surface of the substrate and having different widths in a direction parallel to the first surface of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

Abstract: A GaN device with N2 pre-treatment is provided in the present invention, including a GaN substrate, an AlGaN layer covering the GaN substrate, a p-GaN gate on the AlGaN layer, a TiN electrode on the p-GaN gate, a first dielectric layer on the AlGaN layer surrounding the p-GaN gate, wherein a horizontal spacing is between the first dielectric layer and the p-GaN gate, and an interface between the AlGaN layer and the GaN substrate not covered by the first dielectric layer is subject to N2 pre-treatment, and a second dielectric layer covering on and directly contacting the exposed first dielectric layer, AlGaN layer, p-GaN gate and TiN electrode.

Abstract: A HEMT device including a substrate structure, a channel layer, a barrier layer, a gate electrode, a drain electrode, a first source field plate, a second source field plate, and a dielectric structure is provided. The first source field plate extends from the second side of the gate electrode to the first side of the gate electrode. The second source field plate is located on the first side of the gate electrode and is located between the drain electrode and the first source field plate. There is a gap between the first source field plate and the second source field plate. The first source field plate has an end adjacent to the gap. The thickness of the dielectric structure located directly below the second source field plate is greater than the thickness of the dielectric structure located directly below the end of the first source field plate.

Abstract: The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.

Abstract: A respiratory status classifying method is for classifying as one of at least two respiratory statuses and includes an original physiological parameter inputting step, an original chest image inputting step, a characteristic physiological parameter generating step, a characteristic chest image generating step, a training step and a classifier generating step. The characteristic chest image generating step includes processing at least a part of the original chest images, segmenting images of a left lung, a right lung and a heart from each of the original chest images that are processed, and enhancing image data of the images being segmented, so as to generate a plurality of characteristic chest images. The training step includes training two respiratory status classifiers using a plurality of characteristic physiological parameters and the characteristic chest images by at least one machine learning algorithm.

Abstract: A respiratory status classifying method is for classifying as one of at least two respiratory statuses and includes a training's physiological parameter inputting step, a training's chest image inputting step, a characteristic physiological parameter generating step, a characteristic chest image generating step, a training step and a classifier generating step. The characteristic chest image generating step includes processing at least a part of the training's chest images, segmenting images of a left lung, a right lung and a heart from each of the training's chest images that are processed, and enhancing image data of the images being segmented, so as to generate a plurality of characteristic chest images. The training step includes training a plurality of characteristic physiological parameters and the characteristic chest images by at least one machine learning algorithm.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a plurality of floating gates on it, and an isolation structure between the floating gates. The method includes performing a first etching process to recess the isolation structure and to form an opening between the floating gates to expose a portion of the sidewalls of the floating gates. The method includes conformally forming a liner in the opening. The method includes performing an ion implantation process to implant a dopant into the isolation structure below the liner. The method includes performing a second etching process to remove the liner and a portion of the isolation structure below the liner, thereby giving the bottom portion of the opening a tapered profile.

Abstract: This disclosure provides a semiconductor structure and a method of forming buried field plate structures. The semiconductor structure includes a substrate, buried field plate structures, and a gate. The substrate incudes a first surface and a second surface opposite the first surface. Each of the buried field plate structures include a conductive structure and an insulation structure surrounding the conductive structure. The gate is embedded in the substrate and extend into the substrate from the first surface of the substrate, wherein the gate is configured between the two neighboring buried field plate structures. The conductive structure includes portions arranging along a direction perpendicular to the first surface of the substrate and having different widths in a direction parallel to the first surface of the substrate.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

Abstract: A method of a flash memory controller coupled between a flash memory and an electronic device is provided. The flash memory has a plurality of blocks each having a plurality of pages. The method includes: detecting whether a data unit is formed by a repeated pattern, the data unit being transmitted from the electronic device and to be written into the flash memory or the data unit being read from the flash memory; and making a record of the repeated pattern at a field of the specific table if determining that the data unit is formed by the repeated pattern.

Abstract: A circuit comparing method includes the following operations: detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a first circuit diagram; detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a second circuit diagram; determining at least one difference between several connection relationships of the first circuit diagram and several connection relationships of the second circuit diagram; and outputting the at least one difference.

Abstract: A method of a flash memory controller coupled between a flash memory and an electronic device is provided. The flash memory has a plurality of blocks each having a plurality of pages. The method includes: detecting whether a data unit is formed by a repeated pattern, the data unit being transmitted from the electronic device and to be written into the flash memory or the data unit being read from the flash memory; and making a record of the repeated pattern at a field of the specific table if determining that the data unit is formed by the repeated pattern.

Abstract: A circuit comparing method includes the following operations: detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a first circuit diagram; detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a second circuit diagram; determining at least one difference between several connection relationships of the first circuit diagram and several connection relationships of the second circuit diagram; and outputting the at least one difference.

Abstract: An air-conditioning device includes a plurality of duct modules and a power module. The duct modules each have a temperature-adjusting unit, an air flow-guiding unit and an energy transmission module. The temperature-adjusting unit is disposed at the second end of the duct module, and has opposing first and second side surfaces. The air flow-guiding unit is disposed at the duct module. The energy transmission module is disposed between the temperature-adjusting unit and the air flow-guiding unit. The power module provides operational power for the duct modules. The air flow-guiding unit guides air flow to enter from the first end of the duct modules. The energy transmission strength of the air flow is enhanced from the energy transmission module. The air flow passes through the first or second side surface of the temperature-adjusting unit, and exists from the second end of the duct modules.

Abstract: An air conditioning device includes a duct module and a heat exchange module. The duct module includes a temperature control unit disposed at a second region of the duct module, a first air flow guide unit disposed between a first region and the second region of the duct module, and a first liquid energy conducting element disposed at the first region of the duct module. The heat exchange module has a delivery duct, an accommodating case, a driver unit, a second air flow guide unit, a heat exchanger and a second liquid energy conducting element. The driver unit drives condensed water to pass through the delivery duct. The second air flow guide unit provides an air flow to the heat exchanger for exhausting waste heat. The second liquid energy conducting element performs heat exchange to cool down.

Abstract: An air conditioning device is provided, including an air duct module having a temperature adjusting unit, an energy conduction component, an airflow guiding unit and a control module. The temperature adjusting unit is disposed in the air duct module and has a first side configured for generating a first temperature range and a second side configured for generating a second temperature range. The airflow guiding unit is disposed in the air duct module. The energy conduction component is disposed in the air duct module configured for conducting the energy generated by the first side or the second side of the temperature adjusting unit. The control module is configured for controlling on-off operations or configurations of the temperature adjusting unit and the airflow guiding unit.

Abstract: An air-conditioning device is provided, having a plurality of duct modules and a power module. Each of duct modules has a first end, a second end opposite to the first end, a temperature adjusting unit, and a first airflow guiding unit. The temperature adjusting unit has a first side configured for generating a first temperature range and a second side opposite to the first side configured for generating a second temperature range. The first airflow guiding unit is disposed at the first end or the second end of the duct module configured for guiding an airflow to enter through the first end, pass through the first side or the second side, and exit from the second end. The power module provides power required for operations of the temperature adjusting unit and the first airflow guiding unit.