Patents by Inventor Yu-Jen Huang

Yu-Jen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110130930
    Abstract: A constant speed control method for a vehicle and a device thereof are disclosed. The constant speed control method includes steps of: firstly examining if a constant speed switch of the vehicle is pressed by an electronic control unit; allowing the electronic control unit to enter a constant speed mode when the constant speed switch is pressed; and sending a signal by the electronic control unit, so as to lock a throttle locking device for maintaining an opening degree of a throttle valve, and to adjust an transmission ratio of an electric continuously variable transmission (ECVT) for maintaining the constant speed driving of the vehicle. The present invention is further related to a constant speed control device for implementing the above method.
    Type: Application
    Filed: November 19, 2010
    Publication date: June 2, 2011
    Applicant: Kwang Yang Motor Co., LTD.
    Inventor: YU-JEN HUANG
  • Publication number: 20110075024
    Abstract: A holder is disclosed, wherein the holder is situated on a circuit board and is used for connecting with an electronic component. The holder comprises an upper surface, a lower surface, and an opening. The upper surface comprises a recess used for laying a flat component, wherein the recess comprises at least one rough area; the lower surface comprises a protruding edge, wherein the protruding edge is connected with the circuit board with glue, and the protruding side and the circuit board delimit a space; and the opening penetrates the upper surface and the lower surface, whereby the gas generated from heating the glue will accumulate in the enclosed space, and the gas will then escape through the opening and out through at least one of the rough areas.
    Type: Application
    Filed: December 9, 2010
    Publication date: March 31, 2011
    Inventors: Chia-Ching Tso, Yu-Jen Huang, Chih-Hao Lin
  • Publication number: 20100245242
    Abstract: An electronic device and a method of operating a screen are disclosed; the touch screen has a display area and a non-display area, and the method includes steps as follows. First, a first sensing signal is generated when a designator controls a pointer on the non-display area. Then, a second sensing signal is generated when the pointer is moved from the non-display area to the display area. Then, a third sensing signal is generated when the pointer is moved on the display area. Last, a user interface is opened in the display area when a processing module receives the first, second and third sensing signals sequentially.
    Type: Application
    Filed: March 31, 2010
    Publication date: September 30, 2010
    Inventors: Yi-Hsi WU, Huang-Ming Chang, Yu-Jen Huang, Hong-Tien Wang
  • Patent number: 7610535
    Abstract: Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors on the PCBA should correspond to the pins of a test I/O module. And use the wiring report generated by an auto test program generator to correspond the pins of the test I/O module to the pins of the connectors which are accessed by boundary scan. Thus the IC of the test I/O module would not have any unused pin between any two consecutive pins wired to the connectors of the PCBA.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: October 27, 2009
    Assignee: Function Research Inc.
    Inventors: Yu-Jen Huang, Chih-Hung Lin
  • Patent number: 7596728
    Abstract: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: September 29, 2009
    Assignee: Faraday Technology Corp.
    Inventors: Tsu-Wei Tseng, Yu-Jen Huang, Chun-Hsien Wu, Jin-Fu Li, Chien-Yuan Pao
  • Publication number: 20090097342
    Abstract: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 16, 2009
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Tsu-Wei Tseng, Yu-Jen Huang, Chun-Hsien Wu, Jin-Fu Li, Chien-Yuan Pao
  • Publication number: 20080317564
    Abstract: A wafer supporting device of a sputter apparatus includes a pedestal positioned in a sputtering chamber and used to load a wafer for sputtering, a deposition ring having a recess positioned on a peripheral portion of the pedestal, and a cover ring positioned on the pedestal and the deposition ring. The cover ring has a gate corresponding to the recess.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Inventors: Chi-Piao Cheng, Li-Chun Liang, Yu-Jen Huang, Been Chen
  • Publication number: 20080270857
    Abstract: Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors on the PCBA should correspond to the pins of a test I/O module. And use the wiring report generated by an auto test program generator to correspond the pins of the test I/O module to the pins of the connectors which are accessed by boundary scan. Thus the IC of the test I/O module would not have any unused pin between any two consecutive pins wired to the connectors of the PCBA.
    Type: Application
    Filed: May 14, 2007
    Publication date: October 30, 2008
    Inventors: Yu-Jen Huang, Chih-Hung Lin
  • Publication number: 20050135071
    Abstract: The present invention provides a package structure of optical sensitive device. The package structure includes a silicon substrate, an optical sensitive device, a supporting pad, a transparent plate and a plurality of conductive wires. The optical sensitive device is positioned on the silicon substrate, and the transparent plate is fixedly positioned on the supporting pad and corresponds to the optical sensitive area of the optical sensitive device. The transparent plate can be positioned on the substrate, and the electrical wires are electrically connected between the optical sensitive device and the substrate.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Billy Wang, Bill Chang, Yu-Jen Huang, Chao-Yen Hsieh
  • Publication number: 20050133888
    Abstract: A package substrate having a chip on a substrate has a die pad on the substrate. The chip is attached on the die pad via ah adhesive. A plurality of gold contacts is distributed on the die pad for electrically connecting to the chip. A plurality of traces is distributed around the die pad to connect to the chip via wires. An adhesive dike is formed between the die pad and the traces to prevent the adhesive from flowing out of the die pad when the chip is attached on the die pad.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Bily Wang, Bill Chang, Yu-Jen Huang, Chao-Yen Hsieh
  • Patent number: D511333
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 8, 2005
    Assignee: Lite-On It Corporation
    Inventors: Te-Hsiung Lai, Yu-Jen Huang
  • Patent number: D483729
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: December 16, 2003
    Assignee: Lite-On It Corporation
    Inventors: Yu Jen Huang, Hung Yuan Chen