Patents by Inventor Yu-Jen Tseng

Yu-Jen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150325542
    Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 12, 2015
    Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9111817
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9105530
    Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar width, and the UBM width is greater than the pillar width.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 8853002
    Abstract: Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jen Lin, Ai-Tee Ang, Yu-Jen Tseng, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20140252598
    Abstract: A package and method of making the package are provided. An embodiment package includes an integrated circuit supporting a conductive pillar, a substrate having a landing pad on each embedded metal trace, a landing pad width greater than a corresponding embedded metal trace width, and a conductive material electrically coupling the conductive pillar to the landing pad. In an embodiment, the landing pad overlaps the metal trace in one direction.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Yu-Jen Tseng
  • Publication number: 20140193952
    Abstract: Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jen Lin, Ai-Tee Ang, Yu-Jen Tseng, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20140110847
    Abstract: A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Jen TSENG, Yen-Liang LIN, Tin-Hao KUO, Chen-Shien CHEN, Mirng-Ji LII
  • Publication number: 20140077365
    Abstract: An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.
    Type: Application
    Filed: May 29, 2013
    Publication date: March 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20140077359
    Abstract: An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap.
    Type: Application
    Filed: January 4, 2013
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Chun Tsai, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 8664041
    Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Tin-Hao Kuo
  • Publication number: 20130270693
    Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Tin-Hao Kuo
  • Publication number: 20090168177
    Abstract: The active reflective warning apparatus includes a transparent housing having a clear surface, a glittering retroreflective sheeting applied on the clear surface of the transparent housing for reflecting an external light, and a light-emitting unit disposed in the transparent housing. The light emitting from the light-emitting unit may emit through the clear surface and the glittering retroreflective sheeting.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Inventors: Yu-Jen Tseng, Aileen Shaw